Specifications
Fabric Density
Up to 138K LUTs (GW5A(S)(T)-138); up to 23K LUTs (GW5A-25)
Family Variants
GW5A (traditional FPGA), GW5AT (transceivers), GW5AR (integrated RAM), GW5AS (embedded MCU), GW5AST (RISC-V AE350), GW5ART (transceivers), GW5A/GW5AT automotive grades
Block SRAM
Single-port, semi-dual-port, true dual-port and semi-dual-port modes with byte write enable
ECC Support
Error detection and correction in block SRAM plus configuration memory soft error recovery (CMSER)
DSP Blocks
12x12, 27x36 and 27x18-bit multiplier modes with a 48-bit accumulator
DSP Features
DSP cascading, embedded pipeline and bypass registers, pre-addition for filter functions, internal feedback loop and barrel shifter
Clocking
Up to 16 global clocks, up to 6/12 high-performance PLLs, up to 16/24 high-speed edge clocks
GPIO Drive Strength
Selectable 4 mA, 8 mA, 12 mA, 16 mA and 24 mA drive
GPIO Features
Bus keeper, pull-up/pull-down, open drain, hot socket, input hysteresis and slew-rate control
On-Chip ADC
60 dB SNR with 1 kHz signal bandwidth, flexible X-channel oversampling, no external voltage source required
SerDes (GW5AT/GW5AST)
270 Mbps to 12.5 Gbps operation with CDR, dedicated RX and TX channels, integrated 8b/10b encoder/decoder
PCIe Hardcore
PCIe 2.0 hardcore with x1, x2, x4 and x8 lane configurations, root complex and endpoint support
Hard Processor
GW5AST devices integrate a hardcore RISC-V AE350_SOC processor
MIPI D-PHY RX Hard PHY
20 Gbps D-PHY RX hard PHY with 8 data lanes plus 2 clock lanes at 2.5 Gbps per lane (GW5A(S)(T)-138)
MIPI C-PHY
MIPI C-PHY RX/TX hardcore, one quad supporting up to three three-wire data lanes at up to 2.5 Gsps per lane
MIPI Link Layers
Built-in MIPI DSI and MIPI CSI-2 RX link layer IPs with SoT HS-Sync, word and lane alignment
Memory Interface
DDR3 memory interfacing built into the Arora V fabric
Configuration
JTAG, SSPI, MSPI, SERIAL and CPU configuration with background programming, SPI flash programming/boot and multi-boot
Security
Bitstream encryption and security with OTP and a unique 64-bit DNA identifier per device
Development Tools
GOWIN EDA — synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyzer
Overview
The GOWIN Arora V series is a SRAM-based FPGA line that increases logic resources, interface bandwidth and performance while keeping power consumption low. Devices span from the 23K-LUT GW5A-25 up to the 138K-LUT GW5A(S)(T)-138, with DDR3 interfacing, 12.5 Gbps CDR-based SerDes supporting multiple protocols and flexible packaging options.
Because the family shares a common EDA flow and IP ecosystem, designs can be scaled from low-cost sensor-bridge roles up to server and communications line cards that combine 12.5 Gbps serial links, PCIe 2.0 hardcore endpoints and MIPI D-PHY/C-PHY camera interfaces on one device. The GW5AST variant adds a hardened RISC-V AE350_SOC for control-plane work alongside the programmable fabric.
For edge AI and machine-vision designs the Arora V family pairs high DSP-to-logic ratios with a hard MIPI receive PHY and PCIe endpoint, which is what makes it suitable as a real-time sensor-fusion, video-preprocessing or accelerator-glue device in front of a host SoC or a discrete AI accelerator.
Key Benefits
High performance per watt with SRAM-based fabric, dynamic power management and a 12.5 Gbps SerDes that keeps interface bandwidth high without a separate PHY. Integration of PCIe 2.0 hardcore, MIPI D-PHY/C-PHY hard PHYs, ADC and DDR3 reduces external component count. Design portability across a single EDA flow from 23K to 138K LUTs protects the investment as requirements grow, and security features such as bitstream encryption, OTP and a unique 64-bit DNA identifier support anti-cloning and device authentication.
Applications
Communications line cards and small cells, server and data-centre bridging and interface expansion, machine-vision and industrial imaging pipelines, automotive camera and display aggregation, medical imaging front-ends, LED display control, and real-time AI edge preprocessing where deterministic latency matters more than raw TOPS.
Request a Quote — GOWIN ARORA V FPGA (GW5A / GW5AT / GW5AR) — 138K-LUT SRAM FPGA WITH 12.5 GBPS SERDES
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