Specifications

Family

Microchip PolarFire SoC (MPFS)

Device

MPFS250T

MPNs (package variants)

MPFS250T-1FCG1152E (1152 FCBGA) · MPFS250T-1FCSG536I (536 FCSG)

Logic Elements

254,000 LEs (254KLE)

CPU Subsystem

5-core RISC-V: 1x 64-bit E51 monitor core + 4x 64-bit U54 application cores

CPU Features

RV64GC, coherent 2 MB L2 cache, deterministic L1 memory

Linux Support

SMP Linux (Yocto / Buildroot) on the U54 cluster

Math Blocks

Up to 784 18x18 multiply-accumulate (MACC) blocks

Total RAM

Up to 17.6 Mb LSRAM + 10.8 Mb uSRAM

Transceivers

Up to 4x SerDes lanes, 250 Mbps - 12.7 Gbps

Memory Interface

DDR4 / DDR3 / LPDDR4 / LPDDR3 hard controller

Fabric Performance

Up to 500 MHz (fabric), 667 MHz (DDR4)

Security

Physically unclonable function (PUF), DPA-resistant crypto, secure boot, Athena TeraFire crypto processor

Reliability

SEU-immune FPGA configuration (flash-based, no external config memory)

Temperature Grade

E (-40 to +100 °C Tj) / I (-40 to +100 °C Tj) per suffix

Package Options

1152-ball FCBGA and 536-ball FCSG

Power

Low static power — flash-based fabric draws no inrush configuration current

Target Use

Industrial, automotive, defence and space-adjacent designs

Overview

The Microchip PolarFire SoC MPFS250T is a mid-range SoC FPGA that combines a flash-based FPGA fabric of 254,000 logic elements with a five-core 64-bit RISC-V CPU subsystem — one E51 monitor core plus four coherent U54 application cores with a 2 MB L2 cache.

Because the configuration fabric is flash-based rather than SRAM-based, the device is immune to single-event upsets in its configuration memory and needs no external configuration PROM, which simplifies board design and improves boot reliability in industrial and defence equipment.

The 250T is the largest device in the current MPFS family line-up and is supplied in a 1152-ball FCBGA for full I/O and SerDes access, or a 536-ball FCSG package for compact designs. Microchip's PolarFire SoC ecosystem (Icicle Kit, Video Kit, Discovery Kit) provides reference hardware for bring-up.

Key Benefits

Deterministic RISC-V CPU cluster tightly coupled to the fabric, SEU-immune flash configuration, DPA-resistant security with a physically unclonable function, and up to 4 SerDes lanes at 12.7 Gbps for mid-range line-rate protocols.

Applications

Industrial motor and servo control, secure networking and TSN endpoints, machine-vision pre-processing, defence and avionics compute, space-adjacent payloads, and functional-safety platforms needing RISC-V determinism.

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Related Products

Microchip PolarFire SoC Icicle Kit — MPFS-ICICLE-KIT Microchip PolarFire SoC Video Kit — MPFS250-VIDEO-KIT Efinix Titanium Edge FPGA