Specifications
Family
Lattice ECP5 — low-power FPGA with SERDES and hard PCIe support
Device
LFE5U-45F (ECP5-45)
MPNs (package / speed variants)
LFE5U-45F-6BG256C (-6BG256I) · LFE5U-45F-7BG256C · LFE5U-45F-6BG381C (-7BG381C) · LFE5U-45F-6BG554C (-7BG554C) · LFE5U-45F-8MG285C
Architecture
LUT4-based ECP5 fabric with distributed memory and embedded block RAM
Fabric Capacity
43,800 LUT4 elements (marketed as 45K class) and 43,800 flip-flops
EBR SRAM
1,944 Kb of embedded block RAM
Distributed RAM
303 Kb in distributed memory
Multipliers
108 × 18 × 18 sysDSP multiplier-accumulator slices
SERDES
4 SERDES channels supporting up to 5 Gbps line rates
PCI Express
PCIe Gen2 x1/x2/x4 hard block on the ECP5-45 (with SERDES)
Clock Resources
Up to 8 PLLs/DLLs with clock dividers, plus dedicated edge clock networks
I/O
Up to 316 user I/O; LVCMOS, LVDS, SSTL, HSTL and MIPI D-PHY capable I/O pairs
Configuration
SRAM-based — loaded from external SPI flash or host; multiple configuration images supported
Security
Bitstream encryption with on-chip AES key storage; configuration lock
Power
Low static power from the 28 nm process; -8 low-power speed grades available
Packages
BG256 (caBGA), BG381, BG554, MG285, TG144
Temperature Grades
C (commercial 0 to +85 °C) and I (industrial -40 to +100 °C)
Target Use
Embedded vision with MIPI cameras, industrial networking, SERDES bridging, motor control and 4K video pipelining
Overview
ECP5 is Lattice's small-to-mid density FPGA line, built for designs that need real SERDES and MIPI D-PHY capability without UltraScale-class power or cost. The LFE5U-45F offers 43,800 LUT4 elements, 1,944 Kb of embedded block RAM and 108 sysDSP 18 × 18 multiplier-accumulator slices.
Its four SERDES lanes support up to 5 Gbps line rates and, together with the hard PCIe Gen2 block, let the device act as an interface bridge, a MIPI-to-PCIe camera aggregator or a multi-lane industrial link endpoint. The open-source Yosys/nextpnr/Project Trellis flow also supports ECP5, which has made it popular in open-hardware designs.
Key Benefits
Four SERDES lanes and hard PCIe Gen2 in a low-power FPGA at a fraction of high-end FPGA power. 108 sysDSP slices and MIPI D-PHY-capable I/O handle camera and sensor pipelines directly. Open-source toolchain support (Yosys / nextpnr / Project Trellis) alongside the vendor flow.
Applications
Embedded vision with MIPI CSI-2 cameras, industrial Ethernet and SERDES bridging, motor and motion control, video format conversion and 4K pipelining, and open-hardware platforms requiring a documented bitstream toolchain.
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