Specifications
Compute Fabric
Hybrid LUT4/LUT6 architecture for efficient logic packing, higher utilisation and improved critical-path performance
Density Range
6K to 90K logic elements across the GW3A family
GW3AT-6K Logic
6,912 LUT4 (1,728 LUT6) with 16,912 flip-flops
GW3A-20K Logic
23,040 LUT4 with 23,040 flip-flops
Device Roadmap
GW3A-35K and GW3A-90K devices listed as forthcoming in the family table
Block RAM
16 x 18K-bit BSRAM blocks with 120 blocks on GW3A-20K
Shadow SRAM
54 kb SSRAM on GW3AT-6K; 1080 kb on GW3A-20K
DSP Slices
52 DSP slices on GW3AT-6K with high-precision modes
Clocking Resources
16 global clocks with 2 PLLs (GW3AT-6K) or 4 PLLs (GW3A-20K)
SerDes
1 TX / 4 RX channels at up to 8.5 Gbps on GW3AT-6K
LVDS
1.6 Gbps RX and 2.0 Gbps TX high-speed LVDS connectivity
DDR3 Interface
Up to 1100 Mbps DDR3 support
GPIO Capacity
Up to 70 GPIOs on GW3AT-6K and up to 238 GPIOs on GW3A-20K
Core Voltage
0.9 V / 1.0 V core supply options
Hard Subsystems
Application-specific hard blocks including MIPI D-PHY, DSC engines, eDP interfaces and multi-channel ADC options
Timing Closure
Tightly coupled PLLs, streamlined I/O banks and protocol-aware subsystems for predictable timing closure
Imaging Pipeline Support
MIPI D-PHY and DSC engines plus eDP target embedded display processing and camera input
Overview
GOWIN's Arora III family introduces a hybrid LUT4/LUT6 compute fabric that improves logic packing density and critical-path performance versus a pure LUT4 architecture. Alongside the fabric, GOWIN integrates application-specific hard blocks — high-precision DSP slices, multi-tier SRAM (BSRAM and SSRAM), multi-channel ADC options, MIPI D-PHY and DSC engines, eDP interfaces and high-speed LVDS — to give designers deterministic acceleration for signal processing, control loops, imaging pipelines and video transport.
Devices span 6K to 90K logic elements, with the GW3AT-6K and GW3A-20K already specified and larger 35K and 90K members in the roadmap. The family is positioned as a compact mid-range platform for real-time industrial control, machine vision, embedded display processing and low-latency bridging, where architectural efficiency, subsystem integration and reliable throughput matter more than peak logic count.
For AI-adjacent designs, Arora III is typically used as the deterministic sensor and display front-end: MIPI camera capture, DSC decompression, image preprocessing and low-latency bridging into a host processor or accelerator, rather than as a general matrix-multiply engine.
Key Benefits
Efficient logic packing from the hybrid LUT4/LUT6 fabric improves utilisation and critical-path performance at a given density. Subsystem integration — MIPI D-PHY, DSC, eDP, ADC, DDR3 and SerDes — cuts board area and BOM cost. Predictable timing closure through tightly coupled PLLs and streamlined I/O banks shortens design cycles, and the 6K-to-90K span lets one architecture serve control, imaging and bridging roles.
Applications
Real-time industrial control loops, machine-vision camera front-ends and preprocessing, embedded display processing and video transport, low-latency protocol bridging, motor and motion control, medical and test instrumentation, and LED display control.
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