Specifications

Generation

HBM3 (third-generation high-bandwidth memory)

Vendor

Samsung

Pin Speed

6.4 Gbps per pin

Bandwidth

Up to 819 GB/s per stack

Capacity Options

16 GB (8-Hi) and 24 GB (12-Hi)

24 GB Configuration

12 layers of 10 nm-class 16 Gb DRAM dies

Stack Height

8-Hi and 12-Hi

Organisation

1024

Package

MPGA

Refresh

32 ms

Bus Width

1024-bit per stack (JEDEC HBM3)

Channels

16 pseudo-channels per stack (JEDEC HBM3)

Use Classes

AI training clusters, inference systems, GPUs and HPC accelerators

Design Goal

Balance of throughput and energy efficiency

Ecosystem

HBM3-class GPU and accelerator platforms from major vendors

Datasheet

Available upon request from Samsung

Overview

Samsung HBM3 is the third generation of high-bandwidth memory, delivering 6.4 Gbps per pin and up to 819 GB/s of bandwidth per stack with capacity options of 16 GB (8-Hi) and 24 GB (12-Hi). The 24 GB stack is assembled from twelve layers of 10 nm-class 16 Gb DRAM dies, using a 1024-bit interface and MPGA packaging at a 32 ms refresh interval.

HBM3 was widely adopted across AI training clusters, inference systems, GPUs and HPC accelerators. Its position in the HBM line is as the balance point: substantially more bandwidth and capacity than HBM2E, at a power and cost profile that made it the mainstream base for the first generation of large model accelerators before HBM3E extended pin speeds to 9.6 Gbps and HBM4 moved to a logic base die.

For system designers, HBM3 remains relevant as the memory generation behind a large installed base of accelerators and as a reference point for evaluating the bandwidth and capacity step-ups that HBM3E, HBM4 and HBM4E each introduced.

Key Benefits

819 GB/s per stack. A 28% bandwidth uplift over HBM2E's 3.6 Gbps generation, at 6.4 Gbps per pin. 24 GB per stack. The 12-Hi configuration raises capacity per stack by 50% over the 16 GB 8-Hi option. Proven and widely deployed. HBM3 shipped across AI training, inference, GPU and HPC accelerator platforms. Energy efficient. Designed for throughput per watt in dense multi-stack accelerator packages.

Applications

AI training accelerators, inference accelerators, HPC systems, GPU high-bandwidth memory, multi-stack accelerator packages, and memory subsystem research and evaluation.

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