Samsung HBM4 12-Hi 48GB — Next-Generation AI Memory Stack

Specifications

Overview

Samsung HBM4 is the fourth-generation High Bandwidth Memory standard, doubling the interface width from 1024 bits to 2048 bits relative to HBM3E. That wider channel is what pushes a single 12-Hi stack past the 2 TB/s mark while keeping the per-die clock in a range the package can still cool.

The 12-Hi 48 GB configuration is the mainstream volume part: 12 DRAM die plus a logic base die, delivering 48 GB of capacity per stack. A 1c (10nm-class) DRAM process is paired with an in-house logic base die, which Samsung states gives it better control over the interface timing versus an outsourced base die.

For AI training and inference systems, HBM4 attaches directly to the accelerator package over a silicon interposer and is shared by the GPU or ASIC across the full 2048-bit bus. Systems are sized in stacks per package, so the 48 GB per stack figure translates directly into accelerator memory capacity.

Key Benefits

2048-bit interface — double the pin count of HBM3E for more than 2 TB/s per stack. In-house base die — 1c DRAM plus Samsung logic die shortens the qualification cycle. Volume availability — mass production since February 2026 with a 50% capacity expansion planned across 2026.

Applications

Next-generation AI training and inference accelerators, hyperscale GPU packages, high-performance computing clusters, and AI server programs that require 48 GB memory stacks with 2048-bit interfaces.

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