Specifications
GW1AN-1 Logic
1,152 LUT4 with 864 flip-flops
GW1AN-1S Logic
1,152 LUT4 with 864 flip-flops in an ultra-compact package
GW1AN-3 Logic
3,200 LUT4 with 3,200 flip-flops
GW1AN-5 Logic
5,408 LUT4 with 4,264 flip-flops
Block SRAM
72 Kbit in 4 BSRAM blocks on GW1AN-1/1S; 90 Kbit in 5 blocks on GW1AN-3/5
Shadow SRAM
10 Kbit on GW1AN-3 and 13 Kbit on GW1AN-5
Integrated Flash
On-chip 4 Mbit NOR flash for configuration and user storage with background programming and multi-image reliability
ADC
Two on-chip ADC channels on GW1AN-5 (none on GW1AN-1/1S/3)
PLLs
1 configurable PLL on GW1AN-1/1S; 2 PLLs on GW1AN-3/5 with output phase adjustment
Core Voltage
1.2 V typical core supply with dynamic clock gating for reduced power
GPIO Capacity
120 GPIOs on GW1AN-1, 44 on GW1AN-1S, 208 on GW1AN-3 and GW1AN-5
Smallest Package
CS30 at 2.2 x 2.8 mm with 0.4 mm pitch (GW1AN-1S)
Package Options
CS30, FN32, QN48 (0.4 mm pitch), LQ100X/LQ144X (0.5 mm), UG256X and PG256X (0.8/1.0 mm, 14-17 mm)
I/O Standards
LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL 3.3, SSTL 3.3/2.5/1.8/1.5, HSTL 1.8/1.5, PCI, LVDS25/E, RSDS, BLVDSE, MLVDSE, LVPECLE and RSDSE
I/O Features
Adjustable drive strength, input hysteresis, bus keeper, pull-up/pull-down and open-drain options with hot socketing support
Logic Architecture
Efficient LUT4-based fabric with built-in support for shift-register implementations
Memory Modes
Block SRAM configurable as dual-port, single-port or semi-dual-port
Configuration Modes
JTAG, AUTO-BOOT, SSPI, MSPI, SERIAL and CPU configuration (package dependent)
Design Migration
Pin compatibility with competitor devices supports drop-in replacement and dual-source sourcing strategies
Overview
The GOWIN Arora GW1AN series packs big-system features into a small-FPGA footprint. Despite the compact die sizes — the smallest package measures just 2.2 x 2.8 mm — the devices include hardened IP subsystems, integrated user flash with background programming and multi-image reliability, and improved ADC performance on the GW1AN-5.
The series targets cost-sensitive, high-volume designs where board space and unit cost dominate: sensor interfacing, simple protocol bridging, power sequencing, LED and display control, and glue logic around a larger SoC or MCU. Core voltage is 1.2 V with dynamic clock gating to keep static and dynamic power low.
A practical advantage for sourcing teams is pin compatibility with competitor FPGA devices, which allows an existing board to be dual-sourced without a redesign — useful where supply continuity of small logic devices is a risk.
Key Benefits
Smallest-in-class packaging from 2.2 x 2.8 mm enables logic where no other FPGA fits. Integrated 4 Mbit flash with background programming removes the external configuration device. Low 1.2 V core with clock gating keeps power budgets small. Pin compatibility with competing devices supports drop-in second sourcing, and adjustable I/O standards from LVCMOS to LVDS and SSTL/HSTL cover mixed-voltage boards.
Applications
Sensor and peripheral bridging, power sequencing and system supervisory logic, LED and small display control, consumer and white-goods control boards, portable and battery-powered instruments, industrial I/O expansion, and low-cost camera or motor-control front-ends.
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