Specifications

1.6T Ethernet

MAC IP for 400G / 800G / 1.6T (IEEE 802.3)

Companion PHYs

1.6T Ethernet PHY, Controller and Verification IP

UCIe IP

UCIe 1.0 / 1.1 / 3.0 PHY and Controller solutions

40G UCIe PHY

UCIe PHY IP on Samsung SF4X

Die-to-Die

D2D Controller IP for multi-die chiplets

HBM Controller

HBM3 / HBM3E Controller IP (JEDEC)

PCIe PHY

PCIe 6.0 PHY NCS on TSMC N3P (x4)

PCIe Gen7

PCIe Express Gen7 PHY IP

Ethernet MAC

100G / 200G / 400G / 800G Ethernet MAC IP

Security IP

ASIL-B PCIe 5.0 IDE security module

Interface Support

PCIe, CXL, streaming, AXI/CXS/CHI-C2C

Process Nodes

TSMC N3P / N3E and Samsung SF4X

Packaging

2.5D / 3D multi-die and chiplet integration

UCIe Standard

Native mapping for PCIe, CXL (I/O, mem, cache)

Ecosystem

Arm + Synopsys subsystem and chiplet integration

Application

AI SoC disaggregation into I/O chiplets

Benefit

Offload connectivity from the main AI compute die

Category

DesignWare interface and subsystem IP

Overview

Synopsys delivers DesignWare interface IP that lets AI SoCs disaggregate connectivity into small I/O chiplets. The 1.6T Ethernet MAC IP, based on IEEE 802.3 for 400G/800G/1.6T applications, is paired with a full PHY, Controller and Verification IP suite, and complements the company’s UCIe die-to-die PHY and Controller solutions.

The portfolio includes a 40G UCIe PHY on Samsung SF4X, D2D Controller IP and HBM3/3E Controller IP, plus PCIe 6.0 PHY on TSMC N3P and PCIe Gen7 PHY. UCIe provides native mapping for PCIe, CXL and streaming protocols, enabling multi-die packaging where PCIe/CXL, Ethernet, UCIe and HBM connectivity are moved off the main AI die onto reusable I/O chiplets.

Key Benefits

Complete 1.6T Ethernet and UCIe IP with PHY, Controller and Verification components. Advanced-node proven on TSMC N3P/N3E and Samsung SF4X. Disaggregation-ready — offload PCIe, CXL, Ethernet and HBM connectivity to reusable I/O chiplets.

Applications

AI SoC and accelerator I/O chiplets, multi-die chipsets using UCIe, 1.6T/800G/400G Ethernet subsystems, HBM3/3E memory interfaces, and PCIe 6.0/7.0 connectivity for datacenter silicon.

Request a Quote — SYNOPSYS 1.6T ETHERNET & UCIE DIE-TO-DIE IP — PHY, CONTROLLER AND VERIFICATION

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