Specifications
Product
Synopsys DesignWare 224G SerDes PHY IP
Per-Lane Rate
224G per lane (PAM4)
Target Links
1.6T Ethernet, PCIe 6.x/7.0 over optics and copper, UALink scale-up
Channel Loss
32 AWG Twinax ~14 dB/m at 56 GHz; total system channel loss 40-50 dB
Reliability Validation
224G IP shown across high-loss channels at DesignCon 2026
DAC Demo
224G PHY IP with 2 m DAC at TSMC OIP 2025
PCIe Demo
First PCIe 6.0 8-lane demo with RC & EP over optical modules and cables
PCIe 6.x Interop
Synopsys and Broadcom PCIe 6.x interop milestone at PCI-SIG DevCon 2025
PCIe 7.0
PCIe 7.0 IP demonstrated over optics for emerging workloads
UALink
UALink 200G 1.0 interface IP; UALinkSec_200 security module
Linear Optics IP
World's first standards-compliant 112G PHY IP for linear optics
Standards
OIF CEI-224G, IEEE 802.3dj 1.6T Ethernet, PCI-SIG PCIe 6.x/7.0
Company
Synopsys (now with Ansys, part of Synopsys)
Overview
Synopsys DesignWare 224G SerDes PHY IP provides the 224G-per-lane electrical layer for 1.6T Ethernet, PCIe 6.x/7.0 and UALink scale-up links in AI infrastructure. The IP has been demonstrated with a 2 m DAC at TSMC OIP 2025 and shown to operate reliably across high-loss channels at DesignCon 2026.
At 224G the Nyquist frequency doubles versus 112G, sharply increasing the impact of channel loss and crosstalk — on the order of 14 dB/m for 32 AWG Twinax at 56 GHz, with total channel loss in a typical system reaching 40-50 dB. Synopsys positions the IP to carry that loss across copper cable, backplane and cabled-optical channels.
The SerDes IP anchors a broader Synopsys interface portfolio for AI: the company demonstrated the first PCIe 6.0 8-lane link over optical modules and cables, showed PCIe 7.0 IP over optics, achieved a PCIe 6.x interop milestone with Broadcom at PCI-SIG DevCon 2025, and offers the industry's first standards-compliant 112G PHY IP for linear optics along with UALink 200G IP.
Key Benefits
224G-per-lane IP enables 1.6T Ethernet and PCIe 7.0 designs; validated across 40-50 dB channels reduces integration risk; optical PCIe demos de-risk cabled-optical system design; UALink plus linear-optics IP covers scale-up fabrics and LRO/LPO modules.
Applications
1.6T Ethernet switch and NIC silicon, AI/XPU SoCs, PCIe 6.x/7.0 over optics, UALink scale-up fabrics, linear-optics (LRO/LPO) module controllers and HPC interconnect.
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