Specifications
SerDes
112G / 224G PAM4 and NRZ
UCIe
Gen3 64 Gbps die-to-die IP subsystem
Bandwidth Density
>20 Tbps/mm
UCIe Controllers
GammaCORE (UCIe 1.1, streaming protocol)
CXL
KappaCORE-64 (CXL 3.0 controller)
PCIe PHY
PipeCORE-64
Protocol Support
AXI-4, AXI-S, CXS, CHI, CHI-C2C
Scale-up / out
800G/1.6T UALink and UEC controllers
Process Nodes
7nm, 6nm, 5nm, 3nm, 2nm; TSMC 3DFabric
Optical DSP
PAM4 and Coherent-lite DSPs
Delivery
IP subsystems and silicon-proven chiplets
Latency / Power
Ultra-low power and latency
Packaging
TSMC 2.5D and 3D advanced packaging
Applications
AI scale-up, scale-out, chip-to-chip interconnect
Overview
Alphawave Semi's foundational AI platform IP addresses both the scale-up (accelerator-to-accelerator) and scale-out (rack-to-rack) connectivity layers of modern AI infrastructure with a ready-to-integrate set of subsystem IP and silicon-proven chiplets.
The portfolio includes 112G and 224G SerDes, a third-generation 64 Gbps UCIe die-to-die IP subsystem delivering over 20 Tbps/mm bandwidth density, the GammaCORE UCIe 1.1 controller, the KappaCORE-64 CXL 3.0 controller and the PipeCORE-64 PCIe PHY.
For rack-level fabrics, Alphawave provides 800G/1.6T UALink and UEC controllers plus PAM4 and Coherent-lite DSPs for optical and electrical links. Delivered as IP subsystems or as chiplets built on TSMC 3DFabric 2.5D/3D packaging across 7nm to 2nm nodes, the platform lets AI silicon designers focus on compute while licensing proven connectivity.
Key Benefits
One IP partner for the full AI connectivity stack from die-to-die UCIe to rack-scale UALink/UEC; silicon-proven 224G SerDes reduces integration risk; >20 Tbps/mm UCIe density maximizes inter-die bandwidth; CXL 3.0 and PCIe PHY IP enable memory and accelerator disaggregation.
Applications
Custom AI accelerator and XPU designs, chiplet-based SoCs, scale-up accelerator fabrics, scale-out rack networks, CXL memory expansion, and data center connectivity silicon.
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