Synopsys HBM4/4E PHY & Controller IP — 12 Gbps, 3 TBps Memory Interface

Specifications

Overview

Synopsys DesignWare HBM4/4E IP is the sixth generation of the company's high-bandwidth memory interface family, comprising a PHY and a controller that together implement the JEDEC HBM4/4E standard for AI and HPC SoCs.

The HBM4 PHY delivers pin bandwidths up to 12 Gbps, giving an overall interface bandwidth of more than 3 TBps. The companion Controller IP is optimized for power, latency, bandwidth and area. Synopsys validated the technology with what it describes as the world's first HBM4 IP test chip, capturing wide-open eye diagrams at 9.2 Gbps — the maximum data rate of currently available HBM devices — while designing the PHY to support future devices at up to 12 Gbps.

The HBM4/4E IP targets AI accelerators, HPC, graphics, networking, ASIC and SoC designs that need the higher per-pin rates and bandwidth density of the HBM4 generation, and fits a multi-die packaging flow alongside Synopsys die-to-die and SerDes IP.

Key Benefits

12 Gbps per pin and >3 TBps more than double HBM3-class bandwidth per stack; first validated HBM4 test chip at 9.2 Gbps reduces integration risk on current parts and leaves headroom to 12 Gbps; power/latency/area-optimized controller suits area-constrained XPUs; single-vendor PHY+controller simplifies bring-up.

Applications

AI accelerator and XPU SoCs, HPC processors, graphics and networking ASICs, edge-inference SoCs and any multi-die design pairing HBM4/4E stacks with compute chiplets.

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