Specifications

Product

Cadence 224G Long-Reach (224G-LR) SerDes PHY IP

Process

TSMC N3E (3nm)

Data Rate

1 Gbps to 225 Gbps across LR, MR and VSR reaches

Architecture

ADC / DSP-based SerDes (112G heritage)

Modulation

PAM4 at VSR and MR

Silicon Status

First-pass silicon success

Channel Loss

~40 dB for copper cable (CR) and backplane (KR); 25-35 dB for C2M/C2C

Target Networks

800G and 1.6T hyperscale datacenter and AI infrastructure

Sibling IP

112G LR SerDes PHY IP (field-proven)

PCIe IP

PCIe 6.0 / 5.0 / 4.0 / 3.0 / 2.0

Multi-Protocol SerDes

64G / 32G multi-protocol SerDes

UCIe IP

Up to 32 Gbps, half-rate and quad-rate, internal PLL, 100 MHz ref clock

UCIe Reliability

Maintenance-mode runtime recalibration across -40 to 125°C

Memory IP

LPDDR5x/5/4x/4, DDR5/4/3 and GDDR7/6

Target SoCs

AI accelerators, hyperscale switch and NIC silicon, chiplets

Overview

Cadence's 224G Long-Reach (224G-LR) SerDes PHY IP extends the company's DSP-based SerDes line to 224G per lane, built on an ADC/DSP architecture and taped out on TSMC's N3E process with first-pass silicon success.

The IP supports data rates from 1 Gbps to 225 Gbps across long-reach, medium-reach and very-short-reach channels, targeting the 800G and 1.6T networks used in hyperscale data centers and AI infrastructure. Its ADC/DSP front end is designed to handle the roughly 40 dB channel loss typical of copper cable and backplane links.

It sits within a broader Cadence high-speed IP portfolio on N3E that also includes 112G LR SerDes PHY, PCIe 6.0, 64G/32G multi-protocol SerDes, UCIe die-to-die IP and DDR5/GDDR7 memory IP — the full interface set for large AI and hyperscale SoCs and chiplets.

Key Benefits

224G per lane halves the lane count for 800G and 1.6T links; ADC/DSP architecture handles high channel loss on standard PCB; first-pass silicon success de-risks integration; full companion IP set (PCIe 6.0, UCIe, DDR5, GDDR7) enables single-vendor high-speed interfaces.

Applications

AI accelerator and XPU SoCs, hyperscale Ethernet switch and NIC silicon, chiplet/die-to-die interconnect, 800G/1.6T optical and copper module controllers, and HPC networking ASICs.

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