Marvell 64 Gbps Die-to-Die Interface IP — HBM & Chiplet Connectivity for XPUs

Specifications

Overview

Marvell's 64 Gbps/wire bi-directional die-to-die interface IP, announced in August 2025, is an industry-first 2nm D2D interconnect (also offered in 3nm) that delivers 32 Gbps of simultaneous two-way connectivity over a single wire. It achieves bandwidth density over 30 Tbps/mm — more than three times that of an equivalent UCIe interface — while a minimal-depth configuration cuts the compute die area needed by roughly 85% versus conventional implementations.

The interface adds adaptive power management that automatically tracks bursty data-center traffic, plus reliability features such as redundant lanes and automatic lane repair to improve yield and reduce bit-error rates. A 3nm 40 Gbps D2D interface, shown at OFC 2026, links HBM and compute die within the same package.

Marvell pairs this interconnect IP with a custom HBM compute architecture that it says enables up to 25% more die area for compute, 33% greater memory capacity and a 70% reduction in memory interface power, developed with memory partners Micron, Samsung and SK hynix. Together these target the memory-interface bottleneck in next-generation custom XPUs.

Key Benefits

64 Gbps/wire with 3x UCIe density concentrates chiplet bandwidth; 85% smaller compute-die interface footprint frees area for logic; adaptive power management matches bursty AI traffic; redundant lanes and lane repair lift yield; custom HBM architecture adds capacity while cutting memory-interface power.

Applications

Custom AI XPU and accelerator chiplets, HBM-to-compute die links in 2.5D/3D packages, scale-up die-to-die fabrics, high-bandwidth memory subsystems and heterogeneous integration.

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