Specifications
Product
HBM4 / HBM4E PHY and Controller IP
Data Rate
12.8 Gbps (exceeds available HBM4 DRAM speeds by ~60%)
Testchip Speed
16-18 Gbps TX, 14 Gbps DRAM read/write (HBM4E stack)
PHY Delivery
Drop-in hardened macro in TSMC N3 and N2
Controller Delivery
Soft RTL macro
Testchip
32-channel PHY + controller, 3nm
DRAM Compatibility
HBM4 and HBM4E stacks
PPA Targets
Aggressive power/performance/area for 3nm nodes
Signal Integrity
Robust TX eye across all channels
Forward Compatibility
Designed for higher DRAM speed grades
Ecosystem
Interoperable with third-party HBM controllers
Applications
AI accelerators, HPC, data center SoCs
Overview
Cadence's HBM4/4E memory interface IP provides a complete memory subsystem solution comprising a PHY and a high-performance controller. The HBM4 PHY is delivered as a drop-in hardened macro in TSMC's N3 and N2 process nodes, while the controller is supplied as a soft RTL macro, giving SoC designers a flexible, silicon-proven path to next-generation high-bandwidth memory.
The IP operates at 12.8 Gbps, roughly 60% above available HBM4 DRAM device speeds, giving designers system margin for future speed grades. Cadence has demonstrated a 32-channel PHY and controller testchip at 3nm reading and writing an HBM4E stack at 14 Gbps DRAM speed with 16-18 Gbps TX, targeting AI accelerators, HPC and data center SoCs and maintaining interoperability with third-party HBM controllers such as Rambus'.
Key Benefits
Margin: 12.8 Gbps exceeds HBM4 DRAM speeds by ~60%. Flexible delivery: hardened N3/N2 PHY plus soft-RTL controller. Silicon-proven: 32-channel 3nm testchip with HBM4E read/write.
Applications
AI accelerator and GPU SoCs, HPC processors, data center compute dies, HBM4/HBM4E memory subsystems.
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