Samsung zHBM — 3D-Stacked HBM-on-Accelerator Memory Architecture

Specifications

Overview

Samsung zHBM is a memory architecture concept that stacks high-bandwidth memory dies vertically, directly on top of an AI accelerator, instead of placing them beside the chip on an interposer. Samsung unveiled the concept model at the Future of Memory and Storage (FMS) 2026 expo in Santa Clara on August 4, 2026.

By flipping the geometry to the Z-axis, zHBM shortens the physical distance signals must travel between compute and memory. Samsung projects that a next-generation interface system built around zHBM will deliver roughly eight times the performance of HBM5, more than ten times its memory density, about three times the energy efficiency, and less than half the thermal resistance.

zHBM is positioned as the third phase of Samsung's HBM roadmap, beyond HBM3E and HBM4/HBM4E, alongside the companion zNAND-O 3D NAND concept. It targets the bandwidth and density demands of large-scale AI training and inference, where memory movement is increasingly the bottleneck.

Key Benefits

~8× HBM5 performance in Samsung's projected next-generation interface; >10× memory density via Z-axis stacking; ~3× better energy efficiency and halved thermal resistance; and a shorter compute-to-memory data path that attacks the AI memory bottleneck directly.

Applications

Large-scale AI training clusters, inference accelerators, high-density AI data-center memory, next-generation GPU and NPU packaging, and 3D-integrated compute-in-memory research.

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