Specifications
Product
SK hynix cHBM (custom HBM)
Concept
HBM stack with a customer-defined logic base die
Base Die Content
Customer-selectable logic — not a fixed JEDEC base die
Embedded Functions
HBM PHY, memory controllers, die-to-die PHYs, custom processing logic
Design Freedom
Customers choose what logic to embed in the base-die area
Compute Benefit
Frees GPU/ASIC die area that would otherwise hold memory interface logic
Demonstrated
CES 2026 — SK hynix cHBM showcase
Related Products
HBM3E 12-high 36 GB (NVIDIA AI server module), HBM4 12-high 36 GB, HBM4 16-high 48 GB
HBM4 16-High
48 GB per stack, shown at CES 2026, successor to 12-high 36 GB at 11.7 Gb/s
Bonding
Advanced MR-MUF (Mass Reflow Molded Underfill)
Wafer Thinning
≈30 µm DRAM wafers to fit 16 layers in a 775 µm JEDEC height
Platform Target
NVIDIA Rubin — up to 8 stacks per GPU, 384 GB class
Market Position
SK hynix holds ≈57 % HBM market share
Customisation Model
Customer-specific base die co-development
Role
AI / HPC accelerator memory
Compliance
JEDEC HBM family
Lead Time
Co-development engagement — contact for availability
MOQ
Co-development engagement
Overview
cHBM (custom HBM) is SK hynix's answer to a structural problem in accelerator design: the HBM physical layer, memory controllers and die-to-die interfaces have historically lived on the GPU or ASIC die, occupying silicon area that could otherwise be compute.
In cHBM that logic moves into a customised base die at the bottom of the DRAM stack. The base die is no longer a fixed JEDEC part — customers define what goes in it, and SK hynix has demonstrated configurations embedding die-to-die PHYs, memory controllers, HBM PHY and custom processing logic.
The commercial effect is that memory becomes a co-designed component rather than a catalogue part: the accelerator vendor reclaims die area for compute, and the memory vendor takes on interface logic that was previously the customer's problem.
Key Benefits
Custom base die — memory interface logic moves off the accelerator die; reclaimed compute area on the GPU/ASIC; customer-defined embedded logic including PHYs, controllers and processing blocks; backed by SK hynix's HBM4 12-high 36 GB and 16-high 48 GB stack roadmap.
Applications
Custom AI accelerator programs where die area is the binding constraint, hyperscaler in-house silicon, and HPC ASICs that need a co-designed memory interface rather than a standard HBM PHY implementation.
Request a Quote — SK HYNIX CHBM — CUSTOM BASE DIE HBM WITH EMBEDDED LOGIC
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