Marvell Photonic Fabric — Optical Rack-Scale Memory Appliance with up to 32TB DDR5 and 1TB HBM Cache

Specifications

Overview

Marvell's Photonic Fabric is an optical interconnect architecture extended from XPU-to-XPU scale-up links into memory disaggregation. Its centrepiece is a Photonic Fabric memory appliance that aggregates sixteen memory modules into as much as 32 TB of DDR5, fronted by approximately 1 TB of HBM acting as a cache rather than an isolated accelerator pool, and shared by up to sixteen hosts as a single memory image. The interconnect reaches 50 metres optically, which is the point: copper scale-up fabrics stop being practical once AI clusters grow past a single rack.

Architecturally this is a photonic-CXL approach to pod-scale memory sharing. CXL provides the host interface while optical links overcome the reach and power limits of an electrical memory fabric, and the design keeps HBM in its proper role as the high-bandwidth cache in front of a much larger, cheaper DDR tier. Flit-based transport converts incoming traffic into flits before transmission to the endpoint. The tiering is aimed squarely at KV cache in long-context, high-concurrency inference, where moving data to an optically attached tier avoids local DRAM capacity limits without falling all the way back to storage-class access — the same gap the rest of the market is attacking with CXL memory modules and SSD-backed caches.

Marvell acquired the Photonic Fabric architecture with Celestial AI, a deal announced in December 2025 and completed on 2 February 2026 for roughly 3.25 billion dollars upfront and up to 5.5 billion with earnouts. It sits alongside Marvell's Ethernet switching, UALink scale-up, CXL/PCIe connectivity and custom XPU businesses as an underlying connectivity layer rather than a standalone optics product. One caveat worth stating plainly: Marvell has said working silicon is still to come, so published capacity, latency, bandwidth and energy figures for the newest configurations are pre-silicon estimates. QS Compute tracks the Marvell memory infrastructure portfolio; contact us for availability, roadmap detail and integration questions.

Key Benefits

Break the rack boundary. Shared memory across multiple racks over up to 50 m of optical fabric. 32 TB of pooled DDR5 per appliance. Sixteen modules, sixteen hosts, one memory image. HBM used properly. ~1 TB of HBM as cache in front of the DDR tier, not a separate pool. Built for KV cache. Up to 2-3x token throughput claimed within the same footprint and power envelope.

Applications

Large-scale AI inference with long context windows and high concurrency, KV cache offload and tiering in rack-scale and multi-rack deployments, memory disaggregation across XPU pods, agentic AI serving where cache residency dominates cost, and data centre architectures moving from single-rack scale-up fabrics to pod-level optical memory.

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