Specifications
Part Number
Teralynx 10
Product Family
Marvell Teralynx Ethernet switch family
Switching Capacity
51.2 Tbps
SerDes
512x long-reach (LR) 112G SerDes
Port Configurations
32x 1.6T · 64x 800G · 128x 400G
Latency
As low as 500 ns; sub-600 ns across all packet sizes
Process
5 nm monolithic
Architecture
Fully programmable with no impact to packet throughput or latency
Programmability
Zero-latency-loss P4-class programmability
Use Cases
Top-of-rack, leaf, spine, AI cluster, network edge
AI/HPC Fit
Designed for AI/ML training fabrics and HPC interconnects
Software
SONiC (Linux Foundation) support, open ecosystem
Availability
Volume production; customer deployments underway
Efficiency
Low power- and cost-per-bit for hyperscale leaf/spine
Key Claim
Industry's lowest published latency for a 51.2T switch
Life Cycle
Production
51.2T switch devices
| Device | Capacity | SerDes | Notes |
|---|---|---|---|
| Marvell Teralynx 10 | 51.2 Tbps | 512x 112G LR | Convertible 32x1.6T / 64x800G / 128x400G, ~500 ns |
| Broadcom Tomahawk 6 | — | — | See the Tomahawk 6 / Davisson page for its configuration table |
Use Case
Teralynx 10 is specified where tail latency matters more than raw port count: distributed training jobs are sensitive to the time packets spend in the fabric, so a switch that holds sub-600 ns at every packet size shortens job completion time and raises GPU utilisation. Because it is programmable without a throughput penalty, the same hardware design can be re-targeted for a new protocol or telemetry format after deployment.
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