Astera Labs Leo X-Series and Leo 2 E/P-Series — CXL Smart Memory Controllers

Specifications

Overview

The memory wall has changed shape. Training runs are bounded by HBM capacity per accelerator, but long-context inference and multi-turn agentic sessions are bounded by something else: how much key-value cache and agent context the system can keep resident and reachable at low latency. Astera Labs' September 2026 Leo launch attacks that second problem directly.

Leo X-Series is the more consequential part. Instead of attaching DRAM to the CPU and letting the accelerator cross a host boundary to reach it, Leo X-Series attaches memory to the scale-up fabric itself — paired with Astera Labs Scorpio Smart Fabric Switches and using PCIe alongside platform-specific protocols. That gives GPU-to-KV-cache access a shorter, higher-bandwidth path than a CPU-attached expansion tier or an NVMe storage tier, and critically it works even when the accelerator does not implement CXL.mem.

Alongside it, the Leo 2 E-Series and P-Series extend CPU-attached memory expansion. Both add PCIe 6.0 x16 or dual x8 host links and CXL 3.2 support with CXL 2.0 backward compatibility, doubling bandwidth and capacity against the previous generation, with up to 768 GB of DDR4 or 4 TB of DDR5 qualified behind a single expander. The E-Series handles capacity expansion; the P-Series adds pooling and sharing for rack-scale memory. QS Compute supplies Leo controllers and the surrounding CXL infrastructure — contact us for part numbers, topology guidance and volume pricing.

Key Benefits

Memory where the accelerator is. Leo X-Series puts a dedicated KV-cache tier on the scale-up fabric instead of behind the CPU. No CXL.mem dependency. PCIe mode lets accelerators without CXL.mem support use fabric-attached memory. Double the previous generation. Leo 2 E and P-Series add PCIe 6, CXL 3.2, and up to 4 TB of DDR5 per expander.

Applications

Agentic AI inference and long-context LLM serving, KV-cache offload tiers, CPU-attached memory capacity expansion, rack-scale memory pooling and sharing, CXL memory appliances, and cost-optimised DDR4 memory tiers in AI servers.

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