Specifications
Part Number
Structera S 30260
Product Family
Marvell Structera S CXL switches
Function
CXL memory-pooling switch
Lanes
260 lanes
Interface
PCIe Gen 6 / CXL 3.x
Connected Hosts
16 or 32 CPUs or GPUs
Maximum Pooled Memory
Up to 48 TB
Aggregate Bandwidth
Up to 4 TB/s
Round-Trip Latency
Under 460 ns
Memory Support
DDR5 and DDR4
Memory Model
Dynamically pooled, shared and disaggregated memory
Prior Generation
Structera S 20256 — CXL 2.0, up to 2 TB/s, 16/32-port (P/N XC50256_3)
Benefit
Breaks the memory wall by decoupling memory from the server
Target Workloads
Agentic AI inference, large in-memory datasets, memory-disaggregated cloud
Deployment
Rack-scale fabric attached to memory chassis
Life Cycle
Announced / sampling
Structera S switch generations
| Switch | Interface | Capacity | Ports |
|---|---|---|---|
| Structera S 30260 | PCIe Gen6 / CXL 3.x, 260 lanes | Up to 4 TB/s, 48 TB pooled | 16 or 32 hosts |
| Structera S 20256 | CXL 2.0 | Up to 2 TB/s | Configurable 16-port / 32-port (XC50256_3) |
Use Case
Structera S 30260 changes the unit of memory allocation from the server to the rack. Instead of sizing each node for its peak footprint, an operator builds a pool of up to 48TB and lets 32 hosts attach to it dynamically, so memory can be moved from a node that is idle to one that is thrashing — without a reboot or a re-cabling. Sub-460 ns round trip and 4TB/s aggregate is what makes that pool usable for AI inference rather than only for cold data.
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