Specifications
Part Number
CN103 (CN103XX family)
Product Family
Marvell OCTEON 10 DPU platform
CPU Complex
Up to 8x Arm Neoverse N2 cores
Process
TSMC 5 nm
SerDes
56G SerDes
Integrated Switch
Up to 1 Tbps, 16x 50GbE ports plus host ports
Ethernet Rates
1/10/25/50/100/200/400GbE
Memory
DDR5
Host Interface
PCIe 5.0
Crypto
True inline IPSec/SSL hardware acceleration, 80 Gbps
ML/AI
Hardware ML/AI accelerator (100x over software processing)
Packet Processing
VPP-based hardware accelerators, up to 5x
Power
25 W typical
Performance
SPECint 2017 rate 36.5 (≈1.5 SPECint per watt)
I/O
USB 3.1, XSPI, eMMC, SPI, UART, I2C, GPIO
Use as
Offload DPU for a host, or primary SoC in a smartNIC/router
Life Cycle
Production
OCTEON 10 CN102 vs CN103
| Part | Cores | SerDes | Target |
|---|---|---|---|
| CN103 | Up to 8x Neoverse N2 | 56G | High-throughput DPU / 400GbE routers and firewalls |
| CN102 | Up to 8x Neoverse N2 | 10G | Cost & power optimised entry devices |
Use Case
CN103 lets a single chip replace a separate control-plane CPU plus a switch ASIC in an appliance: the integrated 1 Tbps switch gives 16x 50GbE-class ports without an external device, while the Neoverse N2 cores run the control plane and the inline crypto engine terminates IPSec/SSL at line rate. In a data centre it is deployed as an offload DPU in front of the host CPU, or as the primary processor in a 400GbE firewall, load balancer or SONiC switch.
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