Specifications
Ordering Part Number
DPUs-2Q400-64S64E64P
Product Family
AMD Pensando Salina 400 DPU
Compute Complex
16x Arm Neoverse N1 cores
Packet Engine
P4-programmable 232 P4 MPU (microsecond latency, millions of flows)
Memory
64 GB DDR5-6400 with ECC (up to 128 GB onboard)
Network Ports
2x QSFP112 (NRZ and PAM4)
Port Configurations
2x 400GE · 4x 200GE · 4x 100GE · 4x 50GE · 4x 25GE
RoCE Support
RoCEv1 and RoCEv2 on L2/L3 networks
Host Interface
PCIe Gen5.0 x16 (single host); multi-host up to two
Form Factor
Full-Height, Half-Length (8 in), single slot
Bracket
Tall bracket fitted; short bracket supplied as accessory
Management
MCTP over SMBus
Security
AES-XTS inline crypto, 128- or 256-bit keys, header/data digest
NVMe-oF
PCIe/NVMe to NVMe-oF PDU conversion, up to 2M+ IOPS
Programmability
P4, C and C++ dataplane services
Virtualization
Up to 1K VFs, VirtIO, tenant isolation
Life Cycle
Production — general availability
AMD DPU and AI NIC comparison
| Product | Ordering PN | Ports | Compute |
|---|---|---|---|
| Pensando Salina 400 DPU | DPUs-2Q400-64S64E64P | 2x QSFP112 400GbE | 16x Arm Neoverse N1 + P4 MPU |
| Pensando Pollara 400 AI NIC | POLLARA-400-1Q400P | 1x 400G / 2x 200G | Programmable RDMA / UEC |
Use Case
Salina 400 is the part to specify when the front-end network of a cloud or AI cluster is saturating host cores: the P4 dataplane runs the vSwitch, the distributed firewall, the IPsec/MACsec tunnel endpoints and the NVMe-oF target on the DPU, while the 16 Arm Neoverse N1 cores host the control-plane agents. Two QSFP112 ports allow dual-rail 400G with independent leaf paths or breakout to four 200G/100G hosts.
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