Specifications
Leo X-Series class
Fabric-attached Smart Memory Controller
Leo X-Series target
Direct AI accelerator-side memory demand
Leo X-Series pairing
Paired with Astera Labs Scorpio fabric switches
Leo X-Series protocol
PCIe and platform-specific protocols for scale-up GPU connectivity
Leo X-Series function
Dedicated memory tier for offloading KV cache and agent context
CXL.mem dependency
Removes the requirement for accelerators to support the CXL.mem protocol
Leo 2 E-Series role
CPU-attached memory expansion
Leo 2 P-Series role
Rack-scale pooled and shared memory
Memory support
DDR4 and DDR5 memory expansion
Host interface
PCIe 6 with single x16 and dual x8 host connectivity
Protocol support
CXL 3.2
Generational gain
Doubles memory bandwidth and capacity versus the previous generation
DDR4 reuse
Allows existing DDR4 modules to be redeployed as CXL-attached capacity
Memory pooling
Dynamic memory pooling across hosts
Tiering
Agentic AI memory tiering combined with Scorpio X-Series switches
Announcement
Announced 15 September 2026 from San Jose, California
Public demonstration
Shown at AI Infra Summit 2026, Santa Clara Convention Center, 15-17 September
Family lineage
Extends the shipping Leo Smart Memory Controller family (Leo CXL CM51652LE / CM61654LE)
Primary workload driver
Agentic AI and general-purpose cloud workloads with growing context windows
Overview
Astera Labs' Leo family addresses the capacity-versus-bandwidth tradeoff that dominates inference infrastructure: AI accelerators need vastly more memory than they can hold, and context windows keep growing. The September 2026 announcement adds three controllers to the family, extending coverage from CPU-attached expansion to directly fabric-attached GPU memory.
The Leo X-Series is the new, more ambitious part. It is a fabric-attached Smart Memory Controller purpose-built for AI accelerator-side memory demand. Paired with Astera Labs' Scorpio fabric switches, it connects memory pools directly into the scale-up fabrics of rack-scale systems so KV cache and agent context can be offloaded to a dedicated memory tier. Crucially, in PCIe mode it removes the dependency on accelerators supporting the CXL.mem protocol, widening the set of hosts that can attach a Leo memory tier.
The Leo 2 E-Series and P-Series serve the CPU-attached side, supporting both DDR4 and DDR5 expansion with PCIe 6 single x16 or dual x8 host connectivity and CXL 3.2. Astera Labs states they double memory bandwidth and capacity versus the previous generation, and they enable DDR4 reuse plus dynamic memory pooling at rack scale. The result is a memory architecture that can be tuned per deployment rather than per socket.
Key Benefits
Right-size memory per architecture — fabric-attached GPU-side capacity with Leo X-Series, and CPU-attached expansion or rack-scale pooling with Leo 2 E-Series and P-Series. PCIe 6 and CXL 3.2 with doubled bandwidth and capacity over the prior generation, plus DDR4 reuse to extract value from existing modules during a severe DRAM shortage.
Applications
Agentic AI and long-context inference deployments, KV cache offload tiers, rack-scale and fabric-attached memory pooling, general-purpose cloud memory expansion, and data centers looking to redeploy DDR4 capacity as CXL-attached memory.
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