Specifications

What a CXL 3.2 memory controller changes at rack level

The CM61654LE is the high-density member of the Leo E-Series: four DDR5 channels at 2 DIMMs per channel, or four DDR4 channels at 3 DIMMs per channel. A CXL 3.2 controller lets a host CPU address that memory as cache-coherent expansion rather than as block storage, which is why it matters for workloads where the working set exceeds the 12- or 16-channel addressable limit of the socket — in-memory databases, graph analytics, and KV-cache offload for long-context inference.

CXL 3.2 also adds fabric-attached memory semantics and port-based routing on top of the CXL 2.0 pool model. In practice that means a memory expander built on the CM61654LE can be pooled and shared between hosts instead of being stranded on one server. Astera Labs' COSMOS stack provides the link telemetry and diagnostics layer — per-lane eye data, link training history and fault isolation — which is what makes a CXL link debuggable in production rather than only in a lab.

Astera Labs products are supplied by QS Compute with B2B pricing, global shipping and short sample lead times for AI data center, edge deployment and industrial integration projects.