Specifications

Two channels in 27 x 27 mm: the module-builder part

The CM51652LE trades channel count and speed for footprint. At 27 x 27 mm with two DDR5 channels it fits an E3.S or add-in-card memory expander where the four-channel CM61654LE would not, at the cost of half the peak bandwidth. That trade is correct when the goal is capacity and pooling rather than raw streaming bandwidth — memory tiering for a hypervisor, or a shared CXL pool that several hosts draw from.

CXL 2.0 is the version that introduced memory pooling with switch-based multi-host access and persistent-memory support; CXL 3.2 (the CM61654LE) adds fabric attach and back-invalidate. Deployments that only need pooled capacity at the lowest silicon cost standardise on the CXL 2.0 part, while those planning switch-fabric memory across racks move to the 3.x controller. Both use the same COSMOS management stack, so fleet telemetry is uniform across a mixed deployment.

Astera Labs products are supplied by QS Compute with B2B pricing, global shipping and short sample lead times for AI data center, edge deployment and industrial integration projects.