Specifications

Why HBM4 moved to 2048 bits

HBM3E kept a 1024-bit interface and gained bandwidth by raising the per-pin rate. HBM4 doubled the interface width to 2048 bits instead, which is a harder engineering problem — twice the PHY, twice the TSV count in the stack — but it decouples capacity growth from pin-rate growth. That is what made a 36 GB 12-high HBM4 stack possible at a pin rate the host PHY could actually close.

SK hynix supplies HBM4 against customer schedules rather than from open inventory, and the reported NVIDIA requirement was revised upward during development to above 11 Gbps per pin, which is why all three vendors resubmitted samples. For a buyer the practical takeaway is that HBM4 allocation is programme-based, not catalogue-based: capacity planning happens against an accelerator programme timeline, and the vendor relationship matters more than a distributor price. Samples and allocation enquiries go through the memory vendor directly, with supply routed through the accelerator OEM.

SK hynix products are supplied by QS Compute with B2B pricing, global shipping and short sample lead times for AI data center, edge deployment and industrial integration projects.