Specifications
Vendor
Montage Technology
M88MX6852
CXL 3.2 memory eXpander controller (MXC)
M88MX5891 / M88MX5851
CXL 1.1 / 2.0 memory eXpander controller (MXC)
Product Class
CXL memory expansion and pooling controller silicon
Protocol
Compute Express Link over the PCIe physical layer
CXL Generations
CXL 3.2 family and CXL 1.1/2.0 family
Function
Terminates a CXL memory link and presents the attached DRAM as addressable system memory
Deployment Form
CXL add-in card, E3.S/EDSFF-class memory module, or platform memory-expansion board
Server Role
Capacity tier behind a high-bandwidth local DRAM tier
Tiering Pattern
MRDIMM/RDIMM as low-latency local memory plus CXL MXC expansion for the cold tier
Primary Workloads
LLM parameter residency, KV-cache offload, RAG vector stores, in-memory databases
Server Class
AI server, general-purpose server, storage server
Why It Matters
Raises per-socket memory capacity without de-populating DIMM slots
Availability
Contact for quote — design-in support and volume pricing on request
Overview
AI servers hit a wall that is neither compute nor storage: the number of DIMM slots a socket can drive. CXL exists to move past that ceiling by putting memory behind a high-speed serial link rather than on the parallel DDR bus, and the Montage memory eXpander Controller (MXC) family is the silicon that terminates that link and presents the far-side DRAM as ordinary addressable memory to the operating system.
Montage has split the line by protocol generation. The M88MX6852 covers CXL 3.2, the newest attach point, while the M88MX5891 and M88MX5851 cover CXL 1.1 and 2.0 designs for platforms still on the earlier revisions. Depending on how the OEM wants to expose the capacity, they sit on a CXL add-in card, an E3.S/EDSFF-class memory module, or a platform expansion board.
The pattern that has settled in AI infrastructure is tiering. A high-bandwidth local tier holds the hot data — model weights being actively read by the accelerator, KV cache, intermediate activations — while CXL memory behind an MXC holds the cold tier: parameters outside the active context window, retrieval corpora and vector indexes. That lets a node carry far more model in memory without cache thrashing or weight re-fetch, and it is why MRDIMM and CXL are usually specified together rather than as alternatives.
QS Compute sources Montage CXL MXC silicon alongside the DRAM, MRDIMM modules and CXL memory expanders that together make up a tiered server memory subsystem.
Key Benefits
Breaks the DIMM-slot capacity ceiling by attaching memory over CXL rather than the parallel bus. Two protocol generations covered — CXL 3.2 on the M88MX6852, CXL 1.1/2.0 on the M88MX5891/5851. Built for tiering behind a high-bandwidth local DRAM tier. Same-vendor roadmap as Montage's MRDIMM and RCD/DB silicon.
Applications
CXL memory expansion cards and E3.S memory modules · LLM parameter residency and KV-cache offload · RAG vector stores and in-memory databases · tiered server memory designs · AI, general-purpose and storage servers
Request a Quote — MONTAGE M88MX6852 / M88MX5891 — CXL MEMORY EXPANDER CONTROLLERS (MXC)
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