Specifications

Overview

The XCENA MX1 is a CXL 3.0 Type-3 computational memory device that pairs high-density memory expansion with thousands of embedded RISC-V cores for near-data processing (NDP). By pushing compute into the memory subsystem, MX1 lets AI and data-centric workloads offload operations without moving data back to the host CPU, easing the memory-wall bottleneck.

MX1 uses PCIe Gen6 as its physical interface and supports up to 1 TB of DDR5 RDIMMs at 8,400 MT/s across four channels, packaged as a full-height full-length (FHFL) add-in card. Enterprise-grade RAS features include advanced DRAM ECC and double-die Chipkill, with CXL 3.2-compliant coherency and hot-page monitoring for memory tiering.

XCENA debuted its MX1 production lineup at FMS 2026 and presented the device at Hot Chips 2026 (co-authored with Samsung Electronics), targeting hyperscale AI infrastructure where memory capacity, bandwidth, and in-memory compute are the new scaling frontier.