Specifications
Part Number
MV-SLA25041-A0-HF350AA-C000
Product Family
Marvell Structera A CXL near-memory accelerators
CXL Generation
CXL 2.0
Compute Complex
16x Arm Neoverse V2 cores
Core Clock
3.2 GHz
Memory Support
DDR5
Channels
4 DDR5 channels
Data Rate
Up to 6400 MT/s
Maximum Capacity
Up to 4 TB
Memory Bandwidth
Up to 200 GB/s
Architecture
“Server within a server” — compute placed at the memory
Workloads
AI inference, DLRM recommendation models, vector search, in-memory databases
Offload Model
Pulls memory-bound work off the host CPU
Inline Compression
Hardware inline memory compression
Positioning
Sits alongside Structera X expanders and Structera S switches
Latency Benefit
Removes the PCIe/CXL round trip for the hot data path
Life Cycle
Production
Structera A / X / S roles
| Device | Part number | Function | Key block |
|---|---|---|---|
| Structera A 2504 | MV-SLA25041-A0-HF350AA-C000 | Near-memory accelerator | 16x Arm Neoverse V2 @3.2 GHz |
| Structera X 2504 | MV-SLX25041-A0-HF350AA-C000 | Memory expansion | 4x Arm Cortex-M7 + 4 DDR5 ch |
| Structera S 30260 | — | Memory pooling switch | 260 lanes PCIe Gen6 / CXL 3.x |
Use Case
Structera A 2504 is specified when a memory-bound stage of a pipeline would otherwise be executed by pulling gigabytes across CXL to the host and pushing results back. Instead the DLRM embedding lookup, the vector-search top-k, or the in-memory database scan runs on the 16 Neoverse V2 cores sitting on the same module as the DDR5, so the host CPU only sees the result. That is the difference between a latency-bound service and a throughput-bound one.
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