MPN: HBC Gen 1 / Gen 2
Qualcomm High Bandwidth Compute
133 TB/s per Card · 3D-Stacked

Near-memory computing architecture bonding compute with accelerated memory bandwidth in a 3D-stacked silicon solution · 133 TB/s per card (HBC Gen 1) · 6× bandwidth per watt versus HBM

HBC Gen 1 — with AI250

First-generation HBC bonded to the Qualcomm AI250 inference accelerator.

HBC Gen 2 — with AI300

Second-generation HBC integrated into the Dragonfly AI300 accelerator platform.

Efficiency vs Alternatives

HBC is engineered to beat both HBM and on-die SRAM on the metrics that govern inference economics.

Memory Wall Strategy

Qualcomm's multi-generation roadmap against HBM, leveraging 3D integration leadership and LPDDR expertise.

Specifications

Vendor

Qualcomm Technologies, Inc.

Product

Qualcomm High Bandwidth Compute (HBC)

Type

Near-memory computing / 3D-stacked memory architecture

Integration

Compute bonded with accelerated memory bandwidth

HBC Gen 1 Bandwidth

133 TB/s per card (designed)

HBC Gen 1 Gain

18× vs AI200 with LPDDR5X

HBC Gen 2 Gain

54× vs AI200 (designed)

Bandwidth / Watt

6× vs HBM (card level)

Capacity / Watt

200× vs SRAM (rack level)

Roadmap

Multi-generation roadmap vs HBM

Gen 1 Sampling

Mid-2027 (with AI250)

Gen 2 Availability

Commercial sampling expected 2028 (AI300)

Stock

Available

Price

Quote

Overview

Qualcomm High Bandwidth Compute (HBC) was announced on June 24, 2026 as the memory pillar of the Qualcomm Dragonfly data center portfolio. HBC is a near-memory computing architecture that bonds compute directly with accelerated memory bandwidth in a 3D-stacked silicon solution, attacking the data-movement bottleneck that dominates modern AI inference cost.

Qualcomm frames HBC as a multi-generation roadmap against HBM. In its first generation, attached to the AI250 inference accelerator, HBC is designed for 133 TB/s per card — an 18× increase in effective memory bandwidth versus the AI200 with LPDDR5X. HBC Gen 2, integrated into the Dragonfly AI300, targets a further stepwise improvement of 54× over AI200.

On efficiency, Qualcomm claims a 6× increase in bandwidth per watt versus HBM (card-level, against published competitor specifications) and a 200× increase in capacity per watt versus SRAM (rack-level). The architecture targets continuous-reasoning agents that need sustained memory bandwidth and real-time responsiveness. HBC Gen 1 sampling with the AI250 is expected mid-2027, with Gen 2 following in the AI300 generation.

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