Specifications
Scorpio P-Series
Broadest PCIe 6 fabric switch family, sized from 32 to 320 lanes
Scorpio X-Series
320-lane open, memory-semantic fabric switch for rack-scale accelerator clusters
PF60321L
PCIe 6, 32 lanes, 21 x 21 mm package
PF60481L
PCIe 6, 48 lanes, 21 x 21 mm package
PF60641L
PCIe 6, 64 lanes, 29 x 29 mm package
PF61601L
PCIe 6, 160 lanes, 45 x 45 mm package
PF63201L
PCIe 6, 320 lanes, 62.5 x 62.5 mm package
PF50641L
PCIe 5, 64 lanes, 29 x 29 mm package for mainstream server designs
Accelerator scalability
X-Series supports up to 80 accelerators per switch with single-hop latency
Hypercast and In-Network Compute
Hardware engines that accelerate collective operations by up to 2x, improving time to first token
Memory semantics
Accelerators access fabric resources through native load/store operations, removing software overhead
Latency
High-radix topology reduces hop count and end-to-end latency while lowering fabric power
KV cache offload
P-Series 160/320-lane switching enables disaggregated KV cache appliances for inference
Server topologies
Yields single-hop connectivity for 8-GPU and 16-GPU all-to-all server designs
Manageability
OpenBMC integration with failure isolation and non-disruptive firmware updates
Telemetry
COSMOS software provides fleet-wide visibility across millions of deployed links
Interoperability
Validated in the Astera Cloud-Scale Interop Lab against diverse PCIe hosts and endpoints
Overview
The Astera Labs Scorpio family is a line of PCIe fabric switches built specifically for AI scale-up rather than general-purpose storage fanout. Two product series cover the spectrum: the P-Series spans 32 to 320 PCIe 6 lanes in a ladder of package sizes, while the X-Series is a 320-lane switch designed for open, memory-semantic rack-scale accelerator topologies supporting up to 80 accelerators per device.
Scorpio switches are unusual in carrying compute of their own. Hardware-accelerated Hypercast and In-Network Compute engines offload collective operations from the GPUs, which Astera quantifies as up to a 2x improvement in collective throughput and a corresponding gain in time to first token and tokens per watt. Memory semantics let accelerators address remote resources with native load/store operations, eliminating a layer of software overhead.
Concrete deployment shapes include single-hop 8-GPU and 16-GPU all-to-all server designs, 64- and 48-lane configurations for GPU-to-NIC peer-to-peer and front-end data ingest, and 160- or 320-lane fabrics for disaggregated KV cache appliances — the workload pattern that dominates long-context inference servers.
Key Benefits
Right-sized PCIe 6 fabrics from 32 to 320 lanes let a single switch cover 8-GPU through 16-GPU servers with single-hop latency to every accelerator. Hypercast and In-Network Compute offload collectives for up to 2x better collective performance and improved tokens per watt. Memory-semantic operation removes software overhead from accelerator-to-accelerator access, and 160/320-lane devices make disaggregated KV cache a practical inference architecture. OpenBMC, COSMOS telemetry and failure isolation keep large fabrics serviceable.
Applications
GPU scale-up fabrics in AI training and inference servers; 16-GPU and 8-GPU all-to-all server backplanes; KV cache disaggregation for long-context inference; front-end NIC ingest and storage fanout; GPU-to-NIC peer-to-peer for scale-out networking; and memory-semantic rack architectures spanning open and platform-specific accelerator protocols.
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