Specifications
Ordering Part Number
POLLARA-400-1Q400P
Product Family
AMD Pensando Pollara 400 AI NIC
Ethernet Speed
Up to 400 Gbps
Port Configurations
1x 400G · 2x 200G · 4x 100G · 4x 50G · 4x 25G
Standards
Ultra Ethernet Consortium (UEC) 1.0 compliant
RDMA
RoCEv2 and fully programmable RDMA transport
Congestion Control
Hardware-based congestion control
Architecture
AMD Pensando P4 programmable dataplane
Role
Front-end (host) NIC and back-end (GPU) scale-out NIC
Form Factor
OCP 3.0
Bracket
Tall bracket fitted; short bracket supplied as accessory
Management
MCTP over SMBus
Performance Claim
Up to 20% higher cluster communication performance vs. competing NICs
Availability Claim
Improves cluster uptime by up to 10%
Ecosystem
Interoperable with open Ethernet switches and optics
Life Cycle
Production — first cloud deployment at Oracle
Pollara 400 vs. Salina 400
| Product | Ordering PN | Standard | Primary role |
|---|---|---|---|
| Pensando Pollara 400 AI NIC | POLLARA-400-1Q400P | UEC 1.0 | GPU scale-out / front-end host NIC |
| Pensando Salina 400 DPU | DPUs-2Q400-64S64E64P | RoCEv1/v2 | Front-end infrastructure DPU |
Use Case
Pollara 400 is the choice when the fabric must carry both the front-end management/tenant traffic and the back-end GPU-to-GPU traffic of an AI node. Because the RDMA transport and congestion-control algorithms are programmable in the P4 dataplane, the same NIC can be re-tuned for a new transport or topology without a hardware change — which is what protects a large cluster from being stranded by a protocol revision.
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