Specifications
Series
Micron HBM4
Stack Height
16-Hi (16-die stacking)
Capacity
48 GB per stack
Interface
2048-bit HBM4 interface
DRAM Process
1-gamma (1γ) DRAM — first HBM to use EUV
Status
Samples shipped to customers
Target Platform
NVIDIA Vera Rubin
2026 Capacity
Sold out under advance contracts
Positioning
Extreme energy efficiency for high-volume inference
Generation
4th-generation High Bandwidth Memory
Comparison
Doubles interface width vs HBM3E (1024-bit to 2048-bit)
Primary Use Case
Inference servers where power cost dominates
Sampling Window
16-Hi samples delivered to NVIDIA alongside SK hynix and Samsung
Mass Production
Ramping after SK hynix; 2026 capacity committed
Overview
Micron HBM4 is the 16-die, 48 GB per stack implementation of the fourth-generation High Bandwidth Memory standard. Demonstrating 16-die stacking capability required Micron to ship HBM4 48GB 16H samples to customers, establishing advanced packaging capability at the top of the stack.
Micron's differentiation is efficiency rather than peak pin speed. The company built HBM4 on a 1-gamma (1γ) DRAM process — the first HBM generation to use EUV lithography — and positions the part for the high-volume inference market where power cost per bit is the dominant hyperscaler concern.
That positioning is reflected in the commercial picture: Micron confirmed at CES 2026 that its entire 2026 HBM4 capacity was already sold out under advance contracts, even with mass production starting later than SK hynix's.
Key Benefits
16-die stacking — demonstrated in customer samples. 1-gamma EUV DRAM — Micron's most advanced DRAM node in an HBM stack. Efficiency first — tuned for inference economics rather than headline bandwidth.
Applications
AI inference servers, power-constrained hyperscale deployments, next-generation GPU platforms such as NVIDIA Vera Rubin, and HPC systems where energy efficiency per bit of memory bandwidth is the purchasing driver.
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