Specifications
Family
Microchip (Microsemi) ProASIC3E — flash-based, non-volatile FPGA
Device
A3PE3000 (also A3PE3000L low-power variant)
MPNs (package / speed variants)
A3PE3000-1FG484I · A3PE3000-2FG484I · A3PE3000-FG896I · A3PE3000L-FG484I · A3PE3000-2PQG208I
Process
130 nm, seven-layer metal CMOS with flash configuration cells
System Gates
3,000,000 (largest density in the ProASIC3E family)
Logic Tiles
75,264 VersaTiles (each a 3-input registered/latched logic cell)
Embedded SRAM
Up to 604 Kb of true dual-port SRAM in 4,608-bit blocks
Configuration
Flash-based, non-volatile — live at power-up, single-chip, no external configuration device
Reprogrammability
In-system reprogrammable over JTAG; configuration retained without power
Security
ProASIC3E flash lock, 128-bit AES decryption with on-chip key, and FlashLock for readback protection
Firm Error Immunity
Flash configuration cells are immune to neutron-induced configuration upsets — no scrubbing required
Clock Resources
Up to 6 global clock networks plus 6 quadrant clocks and PLL options
I/O
Up to 620 user I/O; LVCMOS 1.5/1.8/2.5/3.3 V, LVDS, LVPECL, PCI and SSTL standards
Clock Conditioning
Up to 6 CCC/PLL blocks with programmable frequency synthesis
Packages
PQ208, FG256, FG484, FG896, FG1152
Speed Grades
Standard, -1 and -2 (with L low-power variants)
Temperature Grades
C (commercial), I (industrial -40 to +85 °C), and extended/space grades
Target Use
Safety and mission-critical control, industrial infrastructure, avionics and defence, secure single-chip applications
Overview
ProASIC3E is Microchip's flash-based FPGA family, and the A3PE3000 is its largest member at 3,000,000 system gates and 75,264 VersaTiles, with up to 604 Kb of true dual-port embedded SRAM.
The distinguishing feature is that the configuration cells are flash, not SRAM. The device is therefore live the moment power is applied, needs no external configuration PROM, and is inherently immune to neutron-induced configuration upsets — an important property in avionics, industrial and defence systems where a corrupted bitstream would be a safety issue rather than an inconvenience.
Key Benefits
Single-chip, instant-on operation — no configuration PROM, no boot sequence, no board area for config logic. Configuration-cell immunity to neutron upsets removes the need for scrubbing in high-reliability and elevated-altitude designs. FlashLock, AES decryption and readback protection secure the design inside contract-manufactured hardware.
Applications
Safety-critical industrial control and infrastructure, avionics and defence systems, secure single-chip designs where a readable bitstream is unacceptable, medical equipment, and industrial products requiring instant-on deterministic start-up.
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