Specifications
Family
AMD Xilinx CoolRunner-II CPLD
Device
XC2C256
MPNs (package / speed variants)
XC2C256-7VQ100C (-7VQ100I) · XC2C256-7TQ144C (-7TQG144I) · XC2C256-7CPG132C · XC2C256-7PQG208C · XC2C256-7FTG256C
Process
0.18 µm CMOS with EEPROM-based non-volatile configuration
Macrocells
256 (each with a 40-input function capability via the PLA)
Function Blocks
16 function blocks, 16 macrocells per block
I/O Pins
Up to 173 user I/O
Core Voltage
1.8 V core, 1.5-3.3 V independent I/O banks
I/O Standards
LVCMOS 3.3 / 2.5 / 1.8 / 1.5 V, HSTL-1.5, SSTL-2, LVTTL, 3.3 V PCI
Static Current
Far lower than competing CPLDs — CoolRunner-II holds standby current in the tens of microamps
Power Management
DataGATE input blocking disables selected inputs to cut dynamic power
Clocking
Up to 3 global clock inputs plus 4 product-term clocks; optional 100 MHz dual-edge clock divider
Configuration
Non-volatile — instant-on at power-up, no external configuration memory, reprogrammable in-system via JTAG
Interface Logic
IEEE 1149.1 JTAG boundary scan; real-time reconfigurability
Security
Readback security and bitstream protection on all devices
Packages
VQ100, TQ144, CP132/CPG132, PQ208, FT256, QF32/QFG48
Speed Grades
-6, -7 and -10
Temperature Grades
C (0 to +70 °C), I (-40 to +85 °C)
Target Use
Power sequencing and reset control, bus bridging, glue logic replacing dozens of 74-series parts, PCI/host interface logic
Overview
CoolRunner-II is the ultra-low-power end of the AMD CPLD line: an EEPROM-based, instant-on programmable logic family running from a 1.8 V core with 1.5-3.3 V capable I/O banks. The XC2C256 provides 256 macrocells across 16 function blocks in a conventional PLA architecture.
Because configuration is non-volatile, a CoolRunner-II comes up configured the moment power is applied — which is why it remains the device of choice for power-sequencing, reset control and bus-bridging functions that must be live before an FPGA or processor is clocked. The DataGATE feature lets unused inputs be blocked to cut dynamic power further.
Key Benefits
Non-volatile, instant-on configuration with no boot time and no external config PROM. Ultra-low standby current for always-on control functions. In-system reprogrammable via JTAG, so board revisions can re-route glue logic without a respin.
Applications
Board power sequencing and reset control, voltage-rail supervision, bus and protocol bridging, PCI host interface logic, glue logic consolidation replacing multiple 74-series devices, and legacy CPLD replacement in long-lifecycle industrial designs.
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