Specifications
Product Family
Lattice Mach-N2
Category
Low-power secure control FPGA
Announced
16 September 2026
Primary Role
System control and platform security in infrastructure equipment
Target Applications
Servers, data center infrastructure, communications, industrial systems
Positioning
Extends Lattice's Mach-family secure control FPGA line
Design Flow
Supported by Lattice Radiant design software
Tooling Companion
Lattice Prompt AI-driven FPGA development tool
Security Focus
Platform firmware and secure boot / root-of-trust class functions
Predecessor Line
Lattice MachXO / MachXO5 secure control FPGA families
Vendor
Lattice Semiconductor (NASDAQ: LSCC)
Overview
The Lattice Mach-N2 family, announced on 16 September 2026, extends Lattice's long-running position in secure control FPGAs. These are not high-throughput datapath devices: they are the small, low-power programmable-logic parts that sit alongside a CPU, BMC or ASIC to handle board power sequencing, reset control, glue logic and platform security functions.
Lattice pairs the family with Lattice Prompt, its AI-assisted FPGA development tooling introduced the same day, which targets small and mid-range FPGAs across the design flow. For BOM purposes, Mach-N2 belongs in the control/security tier alongside MachXO and MachXO5, not in the vision/acceleration tier occupied by Avant or ECP devices.
Key Benefits
Purpose-built for system control and security, low-power FPGA fabric for always-on board management, part of a mature secure-control family, and supported by Lattice Radiant + Lattice Prompt tooling.
Applications
Server and storage board management, platform root-of-trust and secure boot, power-up sequencing and reset control, and infrastructure equipment glue-logic consolidation.
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