Specifications
Process
TSMC 7nm FinFET
Family members
AC7t700, AC7t800, AC7t1400 and AC7t1500
System logic cells
730k (AC7t700 / AC7t800) and 1,546k (AC7t1400 / AC7t1500)
6-input LUTs
326k (AC7t700 / AC7t800) and 692k (AC7t1400 / AC7t1500)
2D NoC bandwidth
12 Tbps (700/800) and 21 Tbps (1400/1500), connecting over 80 access points in the fabric
Routing benefit
Reduces routing congestion versus traditional FPGAs by more than 40%
ML processors — INT8
3,456 (700/800) and 10,240 (1400/1500)
ML processors — 4-bit
27,648 (700/800) and 81,920 (1400/1500), integer or block floating point
ML throughput
20.5 INT8 / bFloat16 TOPS (700/800) and 61 TOPS (1400/1500)
ML clock speed
Machine learning processors run up to 750 MHz with co-located block RAM
Number formats
Integer, floating point, bfloat16 and block floating point, with fracturable integer multiply-accumulate
On-chip memory
86 Mb (700/800) and 195 Mb (1400/1500) of LRAM plus BRAM
SerDes
24 x 112 Gbps (700/800) and 32 x 112 Gbps (1400/1500)
GDDR6 memory
6 channels at 1.5 Tbps (700/800) and 16 channels at 4 Tbps (1400/1500)
DDR memory
DDR4 and DDR5 channel support (AC7t700/AC7t800)
PCIe
PCIe Gen5 — 1x8 (700/1400), 1x16 (800) and 2x8/16 (1500)
Ethernet
Up to 8 lanes of 400G (700/800) and 16 lanes with 2 x 400G (1400/1500)
Packaging
42.5 x 42.5 mm BGA (1,677 balls) and 52.5 x 52.5 mm BGA (2,597 balls)
Reference form factor
VectorPath accelerator card with Speedster7t FPGA and GDDR6 memory
Overview
The Achronix Speedster7t family is a 7nm FPGA line built for the two workloads that break conventional FPGAs: high-bandwidth AI inference and 400G networking. Its defining element is a 2D network-on-chip that moves data between I/O, memory, compute blocks and FPGA fabric at up to 21 Tbps through more than 80 fabric access points, cutting routing congestion by over 40%.
Alongside the programmable fabric sit arrays of machine learning processors that natively support 4-bit, 6-bit, 8-bit, 16-bit and 24-bit integer and floating-point formats, including bfloat16 and block floating point. The larger AC7t1400 and AC7t1500 devices pack 10,240 INT8 MLPs running at up to 750 MHz for 61 INT8 TOPS, feeding from 16 GDDR6 channels delivering 4 Tbps of external memory bandwidth.
The interface mix is designed to sit directly in the data path — PCIe Gen5, up to 32 lanes of 112 Gbps SerDes and dual 400G Ethernet — which is why Speedster7t parts commonly appear as inline SmartNIC or inference accelerators. Achronix packages the family on its VectorPath accelerator card for PCIe deployment.
Key Benefits
2D NoC architecture delivers ASIC-level data movement with FPGA programmability, removing the congested routing that throttles traditional high-bandwidth FPGA designs. Dedicated ML processor arrays support the full low-precision format range (4-bit block FP through bfloat16) for efficient quantised inference. GDDR6 memory at up to 4 Tbps and 112 Gbps SerDes keep the fabric fed in inline packet-processing and vision pipelines, while PCIe Gen5 and dual 400G Ethernet make the device a drop-in SmartNIC or accelerator engine.
Applications
LLM and vision inference acceleration at the edge of the network; SmartNICs and DPU offload; 400G/800G line-rate packet processing; machine vision pipelines with GDDR6 frame buffering; 5G/6G wireless and test equipment with JESD204C converter links; and data-center compute offload where power efficiency per inference matters.
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