Specifications

Controller

Silicon Motion SM2524XT

Process

TSMC 6 nm

CPU

Quad-core ARM Cortex-R8

Architecture

DRAM-less (host memory buffer)

Host Interface

PCIe Gen5 x4

Sequential Read

Up to 14 GB/s (internal testing)

Sequential Write

Up to 12 GB/s

Random Performance

Up to 2.5 million IOPS

NAND Channels

4, running up to 4,800 MT/s

Chip Selects

16 per channel

NAND Interface

ONFI 5.2

Power Target

Sub-5 W for client and edge PC form factors

Efficiency

Up to 25% higher performance per watt than the SM2504XT

Positioning

Mainstream PCIe Gen5 for PCs and edge devices

AI Workload Role

Local agent and LLM tasks; KV-cache hosting

Form Factor Fit

M.2 2280 class client and edge modules

Predecessor

SM2504XT (previous-generation DRAM-less controller)

Supply

Controller silicon to SSD vendors; finished modules quoted on request

Overview

The Silicon Motion SM2524XT is a mainstream PCIe Gen5 SSD controller built for PCs and edge devices, and Silicon Motion is explicit about the AI-era reasoning behind it: local agent workloads, on-device language models and KV-cache hosting all put sustained random reads on the SSD that a Gen4 DRAM-less design handles poorly.

The chip is fabricated on TSMC's 6 nm process with a quad-core ARM Cortex-R8 CPU and four NAND channels running up to 4,800 MT/s with 16 chip selects each. Four channels and a quad-core processor work in parallel on flash translation layer scheduling and error correction — the parallelism is where the random-I/O claim comes from, not raw clock speed.

Silicon Motion rates it at up to 14 GB/s sequential read and 12 GB/s sequential write, with up to 2.5 million random IOPS, targeting sub-5 W operation. Against the previous-generation SM2504XT that is up to 25% better performance per watt — a meaningful figure at a moment when DRAM cost is pushing designs toward DRAM-less controllers.

Key Benefits

2.5 million IOPS from a DRAM-less design — four NAND channels plus a quad-core Cortex-R8 in parallel. Sub-5 W and +25% perf/W versus the previous generation, which matters in fanless and battery-adjacent edge enclosures. PCIe Gen5 saturation at 14 GB/s read without a DRAM BOM line. Targeted at AI workloads — local agents, LLM inference and KV-cache hosting on the client or edge node.

Applications

AI PC and edge AI device storage; local LLM and agent workload drives; KV-cache storage on edge inference nodes; mainstream Gen5 M.2 client SSDs; DRAM-less cost-optimised notebooks; industrial edge PCs with tight power budgets.

Request a Quote — SILICON MOTION SM2524XT PCIE GEN5 DRAM-LESS SSD CONTROLLER FOR AI PCS

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