Specifications
Switch Chip
FSL1030M RISC-V network switch SoC
CPU
UX608 with TEE @ 500 MHz (Linux or UCOS dual mode)
10GbE Ports
2× 10GbE SFP+ (2× 10G SerDes)
1GbE Optical
4× 1GbE SFP (4× 1G SerDes)
1GbE Copper
8× 1GbE RJ45 (8 integrated GbE PHYs)
On-chip Packet Buffer
1.5 MB
MAC Address Table
16K entries
VLAN
4K VLANs (port / protocol / subnet / flow based)
ACL
256 entries, ingress and egress
Max Frame Length
16000 bytes (jumbo frames)
Typical Power
4.5 W main control
Redundancy
STP, RSTP, 1+1 / 1:1 port protection, link aggregation
QoS
802.1p / DSCP queuing, 8 queues per port, SP / WRR / DWRR
Timing
Synchronous Ethernet (SyncE) and IEEE 1588
Management
WEB and SSH remote configuration; CLI
Development
JTAG, RS232 and I2C interfaces; open openSBI, u-boot and Linux source
Form Factor
Compact, 1U rack (two units per layer)
Overview
The Milk-V Vega is a compact, low-density open-source 10 Gigabit network switch built on RISC-V switch silicon. It provides a unified platform for broadband, voice, video and surveillance services in data centres, enterprise networks and campus deployments.
The FSL1030M chip integrates eight Gigabit Ethernet PHYs plus 10G and 1G SerDes, and the openSBI, u-boot and Linux kernel sources plus interface SDKs make the platform fully open for secondary development.
Key Benefits
A fully open RISC-V 10GbE switching platform with SyncE/1588 timing, a full L2 feature set and open firmware — ideal for teams that need programmable, auditable network infrastructure.
Applications
Data centre and enterprise access switching, smart campus and industrial park networks, video surveillance backbones, hotels and education networks, and open-source network research.
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