SK hynix 16Gb LPDDR6 at 14.4 Gb/s — 1c nm Low-Power DRAM

Specifications

Overview

SK hynix presented a 16 Gb LPDDR6 device at 14.4 Gb/s per pin at ISSCC 2026, built on its 1c nm DRAM node. The number is not arbitrary: 14.4 Gb/s is the fastest initial LPDDR6 speed bin, and reaching it is roughly a 33 % improvement over LPDDR5X, which tops out at 10.7 Gb/s.

The interesting part of the paper is where the effort went. At these rates the limit is not the memory cell but power delivery and signal integrity across a package and a mobile PCB, so the design work is about power saving and signal handling — how the interface switches and terminates to hold 14.4 Gb/s without a power penalty the platform cannot afford. That is why LPDDR generations track the substrate and packaging roadmap as much as the cell.

Samsung presented a 16 Gb LPDDR6 part at 12.8 Gb/s in the same cycle, so the first LPDDR6 wave ships with two qualified suppliers at different points on the speed curve. LPDDR6 also underpins the LPDDR-based module formats now entering AI servers — SK hynix, Micron and Samsung all ship SOCAMM2 modules — so the generation affects edge AI and on-device inference as much as handsets. QS Compute supplies LPDDR6-generation modules as they reach production.

Key Benefits

14.4 Gb/s per pin — the top initial LPDDR6 bin, 33 % above LPDDR5X. 1c nm node improves power efficiency, which is the real constraint in on-device AI. Two qualified suppliers from the first LPDDR6 wave (SK hynix at 14.4 Gb/s, Samsung at 12.8 Gb/s). Feeds LPDDR-based module formats like SOCAMM2 used in edge and AI-server designs.

Applications

On-device and edge AI inference where memory bandwidth-per-watt is the binding constraint; flagship mobile platforms; thin-and-light AI PCs; and LPDDR-based AI server module formats that trade a socket for bandwidth density.

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