Specifications
Core Count
80 Arm Neoverse V1 cores
Vector Units
2 x 256-bit Scalable Vector Extension (SVE) units per core
Transistor Count
61 billion transistors plus equivalent gates
In-Package Memory
4 HBM stacks, 64 GB total
DDR5 Interfaces
4 DDR5 interfaces supporting 2 DIMMs Per Channel (2DPC)
PCIe
104 lanes of PCIe Gen 5 (product page); the June 2026 product flyer lists 96 lanes in six x16 groups
System-Level Cache
80 MB distributed SLC
Process Node
TSMC N6
Packaging
2.5D advanced packaging, 75 mm x 1.99 mm die area, 5,430-pin package
Bring-up Milestone
First silicon powered on 13 May 2026, followed by a twelve-week functional bring-up
Availability
General availability planned for the end of 2026
Flagship Deployment
JUPITER — the first European exascale supercomputer, based in Germany
Follow-on Product
Rhea2, planned for the Alice Recoque machine in France
Software Ecosystem
Full Arm compiler, library and tooling support
Security Posture
Backdoor-free and kill-switch-free design for sovereign deployments
Overview
SiPearl Rhea1 is Europe's first home-grown HPC processor, developed inside the European Processor Initiative consortium to reduce dependence on non-European silicon. It pairs 80 Arm Neoverse V1 cores with two 256-bit SVE vector units per core and stacks 64 GB of HBM in-package alongside four DDR5 interfaces.
The design deliberately mixes memory technologies: high-bandwidth in-package HBM for bandwidth-bound simulation and AI kernels, plus conventional DDR5 for capacity and cost efficiency, and 104 lanes of PCIe Gen 5 for accelerator attachment. Rhea1 carries 61 billion transistors in a 2.5D package measuring 75 mm x 1.99 mm, manufactured on TSMC's N6 process.
Silicon bring-up began on 13 May 2026 with a twelve-week functional validation phase, and general availability is planned for the end of 2026. Rhea1 is the compute engine for JUPITER, the first European exascale supercomputer, with the follow-on Rhea2 heading to the Alice Recoque machine in France. QS Compute supplies HPC-class CPU platforms, accelerators and rack-scale AI infrastructure — request a quote for sovereign or research deployments.
Key Benefits
Balanced memory: 64 GB in-package HBM plus 4 DDR5 channels (2DPC). Vector throughput: dual 256-bit SVE per core for HPC and AI kernels. Open accelerator fabric: 104 PCIe Gen 5 lanes for GPUs and accelerators. Sovereign supply: European design with no backdoor or kill-switch dependency.
Applications
Exascale and pre-exascale supercomputing, HPC plus AI hybrid workloads, weather and climate simulation, materials science and drug discovery, defence and security research, and European sovereign AI/HPC infrastructure.
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