AMD EPYC 9006 "Venice"

Specifications

The Four Venice Platforms

Venice is not a single processor — it is a family of four product lines on the Zen 6 / TSMC 2nm architecture, launched at AMD Advancing AI 2026 (July 22–23).

• EPYC 9006 SP7 (Flagship) — mainline servers and multi-GPU AI. Up to 256 cores / 512 threads (Zen 6c) or 96 high-frequency Zen 6 cores at up to 5.0 GHz, 16-channel DDR5 at 1.6 TB/s, 128 PCIe Gen 6 lanes per socket (160 in 2P), CXL 3.1, up to 600 W TDP. Available Q4 2026.
• EPYC 9006 SP8 (Mainstream) — enterprise, virtualization, and edge. 8–128 cores, 8-channel DDR5 with 2DPC, 128 PCIe Gen 6 lanes, 1P & 2P, NEBS-friendly, 350–400 W TDP. Available H1 2027.
• EPYC 9006X (Venice-X, 3D V-Cache) — HPC simulation, analytics, and RAG. Up to 96 cores at 5.15 GHz with 1,152 MB of L3 cache via 3D V-Cache (3× L3 per core vs standard SP7). Available H2 2027.
• EPYC 9006 LP "Verano" — AI host nodes for GPU-dense racks. Up to 72 cores / 144 threads, 24-channel LPDDR5X on field-replaceable SOCAMM2 modules, 5 GHz boost. Available H2 2027.

Application

The EPYC 9996 flagship packs 256 Zen 6c cores, 512 threads, and 1,024 MB of L3 cache — the highest-core-count x86 server processor ever produced. AMD claims up to 174% geomean uplift versus the Intel Xeon 6980P, up to 2.2× throughput versus NVIDIA Vera on SPECrate 2026_int_base, and a server-consolidation profile in which 82 2P EPYC 9996 servers replace 1,000 aging Intel Xeon Gold 6258R servers (up to 92% fewer servers and 40% lower 5-year TCO).

QS Compute supplies 6th-gen AMD EPYC 9006 "Venice" processors and server platforms for cloud, enterprise AI, HPC, database, and GPU host-node deployments.