Specifications
P870 class
Six-wide out-of-order superscalar RISC-V application processor
ISA compliance
Meets RVA 23, the contemporary RISC-V application profile
Cluster size
Shared cluster cache supporting clusters of up to 32 cores
P870 design goals
More instructions issued per cycle, more ALU resources and higher branch throughput than the previous generation
P870-D variant
Dense variant for datacenter deployments, pairing with the Intelligence X280 for AI acceleration
X280 class
SiFive Intelligence vector processor for AI/ML and DSP workloads
ISA
64-bit RISC-V with SiFive Intelligence Extensions — custom instructions accelerating AI/ML critical operations
Vector engine
Loosely coupled vector computation pipeline plus ALU, scaling to multi-core and multi-cluster configurations of up to 8 cores
Licensing model
Processor IP licensed to chip designers — configurable cores, not fixed catalogue silicon
Openness
RISC-V instruction set with no licence royalties at the ISA level
AI positioning
Vector extensions and Intelligence Extensions target parallel dataset processing and ML compute at the edge
SoC integration
Cores designed to be integrated with customer accelerators, NPUs and memory subsystems
Use cases
Edge AI inference, storage controllers, networking, automotive and datacenter SoCs
Ecosystem
Supported by RISC-V software toolchains, Linux and standard compilers
Overview
SiFive designs the RISC-V processor cores that other companies put inside their chips. Its AI-relevant line-up has two halves. The Performance P870 is a six-wide out-of-order RISC-V application core meeting the RVA 23 profile, with a shared cluster cache that scales to 32-core clusters — a general-purpose CPU engine for datacenter and infrastructure SoCs, plus a P870-D dense variant aimed specifically at datacenter deployments.
The Intelligence X280 is the AI half. It is a 64-bit RISC-V vector processor implementing SiFive Intelligence Extensions — custom instructions that accelerate the operations AI/ML kernels spend most of their time on — with a loosely coupled vector pipeline and ALU scaling to multi-core, multi-cluster configurations of up to eight cores. That lets a chip designer put vector AI throughput next to a P870 cluster without designing their own DSP.
Because SiFive licenses IP rather than selling catalogue silicon, both cores are configurable and integrate with a customer's own accelerators and memory subsystem. For AI hardware programmes evaluating a non-x86, non-Arm instruction set, the P870 plus X280 combination is the standard RISC-V answer for the CPU and vector-compute tiers respectively.
Key Benefits
RVA 23 compliance with six-wide out-of-order execution gives the P870 contemporary application-class performance in RISC-V, scaling to 32-core clusters for infrastructure SoCs. SiFive Intelligence Extensions and a vector pipeline on the X280 accelerate AI/ML kernels without a custom DSP, and the loosely coupled design scales to 8 cores. IP licensing with configurable cores lets designers match the CPU-to-accelerator ratio to their workload and avoids architectural lock-in to x86 or Arm.
Applications
Datacenter and infrastructure SoCs using the P870-D; edge AI inference where the X280 supplies vector compute; storage and networking controllers; automotive and industrial SoCs; and custom accelerator chips that need a RISC-V host CPU alongside customer-designed NPU blocks.
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