Xsight Labs E1L — Low-Power 200G Programmable DPU

Specifications

Overview

The Xsight Labs E1L is the newest member of the E-Series DPU family. Where the flagship E1 scales to 800G in the core, the E1L brings the same architecture down to as little as 25 W TDP and up to 200 Gbps, so that programmable DPU capability fits inside the power enclosures used by edge, embedded and space-constrained infrastructure where data center class cooling is limited or absent.

The E1L is powered by 8, 16 or 22 Arm Neoverse N2 cores and built on the same TSMC N5 node as the E1. It offers up to 2x DDR5-5200 memory interfaces with inline encryption, line-rate AES-GCM for IPsec offload, and 20 PCIe Gen5 lanes across six dual-mode controllers with SR-IOV. The lowest configuration, an eight-core 100G part, starts at 25 W TDP (15 W typical).

Like the rest of the E-Series, the E1L runs open development frameworks including XDP, DPDK and SPDK with no proprietary SDK, and is Arm SystemReady compliant. That means the same software and tooling span a portfolio that scales from 100G at the edge to 800G in the core on one unified architecture. For AI clusters the E1L is relevant at the network edge of the fabric, where power and space budgets are tight but programmable packet processing and storage acceleration are still required.

Key Benefits

Low power envelope from 25 W TDP (15 W typical) enables DPU offload in edge and embedded racks. Fully programmable via XDP, DPDK and SPDK with no proprietary SDK. Scales with the E-Series from 100G edge to 800G core on one architecture. Inline security with DDR5 encryption and line-rate AES-GCM IPsec offload.

Applications

Edge and embedded AI infrastructure, network and storage offload in space-constrained racks, SmartNIC and DPU roles in AI edge nodes, security and IPsec gateways, and scale-out processing where power is a harder constraint than raw throughput.

Related Products