Specifications
Clock / Data Rate
50 / 100 MHz clock; 100 / 200 Mbps (MUX) data rate
Digital I/O
Up to 640 digital I/O pins (testhead 2)
Vector Memory
32 M vector memory / 32 M pattern instruction memory
Parallelism
Up to 32 sites, any-pin-to-any-site mapping
Device Power Supplies
32 high-performance DPS channels
Timing Accuracy
Edge placement ±300 ps; system ±550 ps
HV Analog
Up to 40 high-voltage I/O pins; HVVI max 1000 V (stacked)
High-Power Analog
MPVI max 320 A pulse mode (ganged)
Mixed Signal
8–32 × 16-bit ADDA channels; 32-CH HDADDA option
Scan
Scan features to 2G depth per scan chain
Software
Chroma CRISP platform (Windows, C++/GUI), STDF output
Cooling
Air-cooled tester-in-a-test-head, small footprint
Positioning
Cost-effective production ATE for fabless, IDM and test houses
Target Devices
High-performance MCU, analog IC, consumer SoC, wafer sort
Per-Pin
Per-pin PPMU and frequency measurement, true test-per-pin architecture
Board
LPC board: 64 digital pins via 16 Chroma PINF ICs (4 timing gen channels each)
Options
ALPG memory test, HVVI, MPVI, VI45, PVI100 analog, AWG/digitizer ASO
Interface
C++ and GUI programming; Windows 7 / 10 host
Overview
The Chroma 3650 is a high-throughput SoC test system with high parallel test capability, positioned as the most cost-effective production ATE for fabless houses, IDMs and test houses. It targets high-performance microcontroller, analog IC, consumer SoC and wafer-sort applications.
Equipped with Chroma's PINF IC and a sophisticated calibration system, the 3650 delivers exceptional timing accuracy within ±550 ps system-wide. Its pattern generator supports up to 32 M pattern instruction memory, matching vector memory depth so pattern instructions can be added for each test vector.
A flexible any-pin-to-any-site mapping architecture enables high-throughput parallel testing on up to 32 sites with no slot boundaries, while an air-cooled tester-in-a-test-head design keeps the footprint small. The optional manipulator enables both package and wafer test.
Key Benefits
Lower cost of test through higher parallelism. True test-per-pin architecture, 640 digital pins and 32 device power supplies per system, per-pin PMU, ±300 ps edge placement, and a broad analog option set spanning AD-DA conversion, high-voltage and high-power test.
Applications
Wafer sort and final test of MCUs, analog and mixed-signal ICs, consumer SoCs; high-volume multi-site production test; parametric characterization with SHMOO and pin-margin tools.
Request a Quote — CHROMA 3650 SOC/ANALOG TEST SYSTEM — HIGH-PARALLELISM ATE
QS Compute — global B2B supply of AI computing hardware, edge AI systems and accelerators. Volume pricing, 15-day sample lead time.
Get Your Quote →