900,000 AI cores · 44 GB on-wafer SRAM · 43 PB/s memory bandwidth · 4 trillion transistors · TSMC 5nm — twice the WSE-3
Faster revision of the WSE-3, doubling clocks across compute, SRAM, fabric, and network.
Third-generation wafer-scale engine that established the 300mm wafer as a single processor.
Second-generation wafer-scale engine, 2.6T transistors on TSMC 7nm.
Cerebras Systems (Sunnyvale, CA)
WSE-3 Turbo wafer-scale engine
Wafer-scale AI accelerator
900,000
250 PFLOPS sparse FP16 (2× WSE-3)
44 GB
43.2 PB/s
53.5 PB/s
300 GB/s
4 trillion
TSMC 5nm
~54 kW (est., doubled vs WSE-3)
WSE-3 (125 PFLOPS, launched 2024)
Aug 2026
Available
Quote
Cerebras Systems pioneered the wafer-scale engine (WSE) — instead of dicing a 300mm wafer into hundreds of chips, it uses nearly the entire wafer as a single processor to deliver dramatically higher bandwidth and lower latency than discrete GPU clusters. The WSE-3 Turbo is a faster revision of the third-generation WSE-3 (launched 2024), doubling performance across the board by raising clocks on the same TSMC 5nm, 4-trillion-transistor design.
Each WSE-3 Turbo integrates 900,000 AI-optimized cores with 44 GB of on-wafer SRAM. Rated compute doubles to 250 PFLOPS of sparse FP16, on-wafer memory bandwidth to 43.2 PB/s, mesh fabric bandwidth to 53.5 PB/s, and off-wafer network bandwidth to 300 GB/s. Cerebras has not disclosed exact power, but the CS-4 rack it targets is built to deliver roughly twice the power of the prior system, implying a per-wafer draw near 54 kW — indicating the company tamed its voltage/frequency curve enough to double clocks without a superlinear power penalty.
The WSE-3 Turbo is the compute heart of Cerebras's first true rack-scale system, the CS-4, where three Turbo wafers are linked into a single 750 PFLOPS rack. Cerebras positions the wafer-scale approach as a latency- and bandwidth-advantaged rival to GPU scale-up systems for large-model training and inference.
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