MPN: Groq 3 LPU · LP30 · LPX Rack
NVIDIA Groq 3 LPU
Language Processing Unit · Inference

500MB on-chip SRAM · 150 TB/s bandwidth · 256-LPU LPX rack · FP8 decode-only · 35× throughput vs Blackwell NVL72

Product Lineup

Groq 3 LPU (LP30)

Purpose-built Language Processing Unit optimized exclusively for autoregressive token generation (decode phase).

LPX Inference Rack

Liquid-cooled rack-scale inference system packaging 256 LPUs into a single deterministic compute fabric.

Hybrid GPU + LPU Deployment

NVIDIA's recommended disaggregated serving: GPUs run prefill + attention, LPUs offload FFN layers for decode.

Specifications

Vendor

NVIDIA (Groq LPU
licensed technology)

Product

Groq 3 LPU / LP30

Type

Language Processing Unit
(inference accelerator)

On-Chip SRAM

500 MB per chip

Memory Bandwidth

150 TB/s per chip

Precision

FP8 (INT8/BF16 unverified)

LPX Rack

256 LPUs · 128 GB SRAM
40 PB/s aggregate

Training Support

No (decode-only)

Throughput

~150 tokens/W
35× vs Blackwell NVL72

Determinism

Flat decode latency
at any batch size

Announced

GTC 2026 · $20B Groq deal

Availability

Early access 2026
GA 2H 2026

Stock

Available

Price

Quote

Overview

NVIDIA introduced the Groq 3 LPU (Language Processing Unit) at GTC 2026, following a $20 billion non-exclusive licensing deal with AI chip startup Groq — the largest NVIDIA has ever paid for technology and personnel. Unlike a GPU, the LPU is not a general-purpose accelerator: it does one thing — autoregressive token generation (the decode phase of LLM inference) — and it does it by replacing HBM with a massive on-chip SRAM pool.

Each Groq 3 LPU packs 500 MB of SRAM at 150 TB/s bandwidth — roughly 45× the bandwidth of an H100's HBM3 (3.35 TB/s) and 7× faster than a Rubin GPU's HBM4. Because decode is fundamentally memory-bandwidth-bound (every token reads the full weight matrix and KV cache), that SRAM wall-breaking bandwidth translates directly into tokens. NVIDIA cites ~150 tokens/watt for 70B FP8 models and 35× throughput improvement versus a Blackwell NVL72 for a 1-trillion-parameter model when paired with Vera Rubin NVL72.

The LPX rack packages 256 LPUs (LP30 chips) with 128 GB of aggregate SRAM and 40 PB/s of aggregate bandwidth, holding a full 70B FP8 model plus KV cache in a single rack with deterministic, flat decode latency. Deployment targets dense LLM serving (7B–70B) using a ~25% LPU / 75% GPU hybrid — GPUs handle prefill and attention math while LPUs offload feed-forward network (FFN) layers to their high-bandwidth SRAM.

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