Specifications
Family
Titanium Edge FPGA devices: Ti40, Ti70, Ti95, Ti125 (+ SiP variants)
Logic Elements
38,925 (Ti40) / 68,218 (Ti70) / 93,200 (Ti95) / 122,792 (Ti125)
Architecture
Efinix Quantum XLR cells
Manufacturing Process
16 nm TSMC
Embedded Memory
1.53 Mb (Ti40) to 5.9 Mb (Ti125) 10K RAM blocks
DSP Blocks
100 (Ti40) / 160 (Ti70) / 210 (Ti95) / 288 (Ti125)
High-Speed I/O
MIPI CSI/DSI up to 2.5 Gbps, up to 147 lanes
SiP Memory
Integrated 512 Mbit HyperRAM + SPI boot flash (Ti125 SiP)
Package
225-ball FBGA 10 × 10 mm (Ti125); SiP 8 × 8 mm
Clocking
Up to 7 PLLs and 32 global clock/control networks
Security
PQC ML-DSA-65, AES-256-GCM, RSA-4096, EC-DSA-384, PUF, TRNG; CNSA 2.0
Reliability
Hardware SEU detection and correction
Tools
Efinity toolchain and Lattice-class RTL-to-bitstream flow
Overview
The Efinix Titanium Edge FPGA family brings low-power programmable logic to constrained edge AI and vision systems. Spanning four densities — Ti40 (38,925 LE), Ti70 (68,218 LE), Ti95 (93,200 LE) and the flagship Ti125 (122,792 LE) — the devices are built on the Efinix Quantum architecture at TSMC 16 nm and cut static power by roughly 50% versus higher-end Titanium parts.
System-in-Package (SiP) options integrate the FPGA die with 512 Mbit HyperRAM and SPI boot flash in an 8 × 8 mm package, reducing PCB footprint by up to 60% for space-constrained edge designs. High-speed MIPI I/O at up to 2.5 Gbps supports multi-sensor vision pipelines, while optional post-quantum cryptography (ML-DSA-65, ML-KEM) and hardware SEU scrubbing deliver secure, reliable operation at the far edge.
Key Benefits
39K–123K logic elements in a low-power 16 nm fabric. SiP integration with HyperRAM and boot flash cuts board area. Post-quantum security and SEU scrubbing for long-lifecycle edge systems.
Applications
Edge AI inference, machine vision and imaging, robotics, medical systems, sensor fusion, industrial vision cameras.
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