Specifications
Family
Agilex 3 FPGA and SoC FPGA devices (C-Series)
Fabric Performance
Average 1.9x higher versus previous-generation Altera FPGAs
Power
Up to 38% lower total power consumption
Process Technology
Intel 7
Architecture
Second-generation HyperFlex FPGA architecture
Processor Subsystem
Dual-core Arm Cortex-A55 HPS at up to 800 MHz
Logic Elements
Up to 135,110 LEs (C-Series M16A package configuration)
Transceivers
Four high-speed GTS transceivers at up to 12.5 Gbps
Low-Voltage Differential Signalling
1.25 Gbps LVDS
Camera Interface
2.5 G MIPI D-PHY
Ethernet
2.5 Gigabit Ethernet
HPS Memory
4 GB LPDDR4 expandable to 8 GB
On-Module Flash
32 GB eMMC expandable to 128 GB
Configuration Flash
1 GB QSPI expandable to 2 GB
I/O Voltage Range
1.0 V to 3.3 V
AI Development
Supported by Altera FPGA AI Suite 25.1 for FPGA-based inference
Security
Hardware-rooted isolation and data integrity for confidential computing
Design Software
No-cost Quartus software licence available
Development Kit
Agilex 3 FPGA and SoC C-Series Development Kit with PCIe Gen3 x4 and DDR4
Availability
In production and available to order
Target Applications
Edge AI, embedded control and industrial designs
Overview
Altera Agilex 3 brings the company's HyperFlex FPGA architecture down into the power- and cost-optimised end of the portfolio. The family delivers on average 1.9x higher fabric performance with up to 38% lower total power consumption than the previous Altera generation, an improvement built on Intel 7 process technology and the second-generation HyperFlex architecture.
I/O bandwidth is specified for modern embedded designs rather than legacy interfaces: four GTS transceivers running to 12.5 Gbps, 1.25 Gbps LVDS and 2.5 G MIPI D-PHY for camera and sensor links. The SoC FPGA variants integrate a dual-core Arm Cortex-A55 hard processor system clocked up to 800 MHz, and the C-Series M16A class supports up to 135,110 logic elements alongside 4 GB of LPDDR4 expandable to 8 GB, 32 GB of eMMC expandable to 128 GB and 1 GB of QSPI configuration flash, all across a 1.0 V to 3.3 V I/O range.
For AI workloads, Agilex 3 and Agilex 5 devices are supported by version 25.1 of Altera's FPGA AI Suite, and the family also demonstrates hardware-rooted isolation and data integrity for confidential computing and tamper-resistant edge inference. Altera has announced production availability across its Agilex device families with Agilex 3 FPGAs ready to order, and a no-cost Quartus licence removes the usual tooling barrier. The Agilex 3 FPGA and SoC C-Series Development Kit provides a production-ready starting point with PCIe Gen3 x4 and DDR4 support for edge AI, embedded control and industrial applications.
Key Benefits
1.9x fabric performance at up to 38% lower power versus the previous Altera generation; integrated Cortex-A55 processor subsystem that removes a discrete host CPU; modern interfaces with 12.5 Gbps transceivers and 2.5 G MIPI D-PHY; FPGA AI Suite 25.1 support for edge inference acceleration; and production availability with a no-cost Quartus licence for low-friction adoption.
Applications
Edge AI inference acceleration; machine vision and multi-camera embedded systems; industrial control and motor drive; secure and confidential computing endpoints; sensor fusion front ends; and cost-optimised control-plane logic in embedded products.
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