ZeroFlap AEC 100G–1.6T · 800G ZeroFlap Optics · Toucan PCIe Gen6 / CXL 3.x 16-lane retimer · OmniConnect · PILOT telemetry
Credo Technology Group (NASDAQ: CRDO) is the company that invented Active Electrical Cables, and its ZeroFlap family is the interconnect layer behind many large AI cluster back-end networks. ZeroFlap AECs are plug-and-play copper cables that replace direct-attach copper with superior bend radius, lighter weight and up to 75% less volume, while guaranteeing zero soft link flaps — the failure mode that disrupts the lossless RDMA fabric AI clusters depend on. The family spans 100G, 200G, 400G, 800G and 1.6T, with the 800G ZeroFlap AEC reaching up to 7 metres so hosts can be cabled directly to switches without optical conversion; 400G and 800G variants cover CLOS and SHIFT configurations between QSFP-DD, OSFP, OSFP-RHS and QSFP112 ends at 3.3V and 0–70°C. Alongside the copper line, Credo ships ZeroFlap optical transceivers (800G class) built on its silicon photonics PICs and DSPs for the same reliability goal at optical reach. For PCIe and CXL, the Toucan retimer is a protocol-aware PCIe Gen6 / CXL 3.x device with 32 bi-directional lanes — 16 upstream and 16 downstream — running at up to 64 GT/s per lane with a channel insertion-loss budget above 45dB at 16GHz Nyquist, 6.5ns latency in low-latency mode, first bit error rate better than 1E-9 before FEC, and flexible 1x16 / 2x8 / 4x4 / 8x2 bifurcation. Toucan has passed PCI Express 6.x compliance and joined the PCI-SIG Integrators List, and is targeted at AI GPU fabrics, PCIe riser cards and backplanes, PCIe AECs and PCIe storage servers. For the memory tier, Credo's OmniConnect addresses AI memory and chip-to-chip interconnect scaling, including the inference memory wall. All three lines expose telemetry through PILOT, Credo's Predictive Link Optimization and Telemetry platform, which adds real-time link health, diagnostics and fault isolation. Credo showcased the full portfolio, including 1.6T ZeroFlap AEC and Toucan Gen6 PCIe AEC with PILOT, at AI Infra Summit 2026 in Santa Clara.
Credo Technology Group
San Jose, California
NASDAQ: CRDO
Inventor of the AEC category
100G / 200G / 400G
800G / 1.6T speeds
Up to 7 m
Zero Flap AECs
Up to 75% less volume
vs direct-attach copper
Zero soft link flaps
for lossless RDMA backends
CLOS and SHIFT
QSFP-DD / OSFP / OSFP-RHS / QSFP112
3.3V supply
0–70°C operating
800G transceivers
SiPho PICs + DSPs
32 bi-directional lanes
16 upstream / 16 downstream
Up to 64 GT/s per lane
Gen6 / 5 / 4 / 3 / 2 / 1
6.5 ns
low-latency mode
>45 dB at 16 GHz
PCIe 6 channel loss
FBER better than 1E-9
before FEC
1x16 / 2x8
4x4 / 8x2 and more
PCIe 6.x Integrators List
CXL 3.x / 2.0 / 1.1 low-latency mode
AI GPU fabrics, PCIe AEC
Risers, backplanes, storage servers
AI memory and chip-to-chip
interconnect, memory wall scaling
Link telemetry, diagnostics
integrated logic analyzer
AI Infra Summit 2026
Santa Clara, booth 810
Request a Quote — pricing available upon inquiry.
Contact SalesAvailable. Contact our sales team for current lead times, volume pricing, and integration support.